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[
VHDL-FPGA-Verilog
]
camera_link
Description:
对camera_link接口传输过来的信号进行格式转换，将16bit并行转换成串行输出-Right camera_link interface transfer over the signal format conversion will be converted into serial 16bit parallel output
Platform:
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1727488
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Author:
徐琪
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