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[VHDL-FPGA-Verilog] vhdl-多功能电子表

Description: 这是一个用vhdl编的多功能电子秒表，可以记录几个人的时间，并且可以在跑秒的时候查看记录。。〔原创〕-This is a series with VHDL multifunctional electronic stopwatch, can be recorded by several people, and that they could run in the second examined the records. . [Original]
Platform: | Size: 5120 | Author: 王继东 | Hits:

[VHDL-FPGA-Verilog] VHDL语言100例详解

Description: VHDL语言100例详解。详细讲解了用VHDL语言进行数字电路和数字系统设计的知识。用100个实例，不仅进行基础的门电路设计，而且还有较为复杂的数字系统设计。这些实例可以直接被调用。-VHDL Elaborates on 100 cases. Detailed account of VHDL for digital circuits and digital systems design knowledge. With 100 examples, not only for infrastructure gate design, but also more complex digital system design. These examples can be called.
Platform: | Size: 6633472 | Author: 穆群生 | Hits:

[VHDL-FPGA-Verilog] 国外的VHDL应用例子

Description: 国外的VHDL应用例子，大家可一好好参考一下！-abroad VHDL Application examples, we can make reference to a properly!
Platform: | Size: 232448 | Author: gjd | Hits:

[VHDL-FPGA-Verilog] VHDL例程

Description: 有关VHDL的大量例程，对学习VHDL编程的人具有很大的帮助，不可不看-lot of routines, to learn VHDL programming of great help, I can not see
Platform: | Size: 168960 | Author: 周 | Hits:

[VHDL-FPGA-Verilog] VHDL程序范例

Description: 这是有关VHDL的一些范例，可以通过范例学习一点东西，巩固自己学过的东西-This is the VHDL some examples, examples can learn something consolidate learned things
Platform: | Size: 5120 | Author: 刘建 | Hits:

[VHDL-FPGA-Verilog] vhdl对数

Description: 对数计算源程序，能够在FPGA中计算某数的对数，VHDL源代码，-right calculating source, the FPGA can be calculated for a number of a few, VHDL source code,
Platform: | Size: 116736 | Author: wl | Hits:

[VHDL-FPGA-Verilog] CK20-VHDL

Description: 经典ＣＫ２０时钟程序，实现了时钟的时，分，秒记数，并可以重调，置０-classic procedures CK20 clock and realized the clock, minute and second count, and can be re-emphasize that the Home 0
Platform: | Size: 4096 | Author: 林海 | Hits:

[Books] VHDL-beststudy

Description: This a set of notes I put together for my Computer Architecture class in 1990. Students had a project in which they had to model a microprocessor architecture of their choice. They used these notes to learn VHDL. The notes cover the VHDL-87 version of the language. Not all of the language is covered (about 95％). You may use this booklet for your own personal learning purposes. You may not use it for profit (eg, selling copies of it, using it in a course for which people pay, etc). If you want to make use of it beyond these conditions, contact me and we can come to some arrangement. -This a set of notes I put together for my Co. mputer Architecture class in 1990. Students ha d a project in which they had to model a microproc essor architecture of their choice. They used t hese notes to learn VHDL. The notes cover the Volume L-87 version of the language. Not all of the lang uage is covered (about 95%). You may use this boo klet for your own personal learning purposes. Y ou may not use it for profit (eg, selling copies of it, using it in a course for which people pay, etc). If you want to make use of it beyond these co nditions. contact me and we can come to some arrangement.
Platform: | Size: 245760 | Author: 罗春晖 | Hits:

[Other] DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE)

Description: 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed.
Platform: | Size: 179200 | Author: 李中伟 | Hits:

[VHDL-FPGA-Verilog] vhdl-examples

Description: 这是eda初学者可以借鉴的两个关于电子频率计的VHDL设计实例-This is the EDA beginners can learn from two of electronic Cymometer VHDL Design Example
Platform: | Size: 11264 | Author: 刘磊 | Hits:

[VHDL-FPGA-Verilog] VHDL-six

Description: 用VHDL语言实现六分频，并且已经通过编译和仿真。由此可举一反三，实现任意偶数次分频。-VHDL six minutes frequency, and has been through translation, and simulation. From this we can draw a number at random dual frequency.
Platform: | Size: 25600 | Author: philohb | Hits:

[VHDL-FPGA-Verilog] canbus_vhdl

Description: 使用方法： 1.拷贝到硬盘，用ISE打开工程文件即可。-Use : 1. Copy to the hard drive, use ISE project documents can be opened.
Platform: | Size: 862208 | Author: lious | Hits:

[Other] canvhdl

Description: can总线控制器的原代码，是用vhdl写的，我没有验证过，不保证正确性。可以作为参考。 -can Bus Controller's original code is written in vhdl, I have not tested, it does not guarantee accuracy. Can be used as reference.
Platform: | Size: 31744 | Author: 吴明诗 | Hits:

[Crack Hack] tcdg[1].vhdl

Description: 直接仿真就可以使用，子密钥的输出采用了优化设计，节省了资源。-direct simulation can be used, the output Subkey using the optimum design, saving resources.
Platform: | Size: 5120 | Author: 张亮 | Hits:

[Software Engineering] VHDL

Description: 基才VHDL状态机设计的智能交通控制灯设计有需要的可以看一下-only VHDL-based state machine design and intelligent traffic control lights need to design can look at the
Platform: | Size: 139264 | Author: 杨树茂 | Hits:

[Software Engineering] filter-vhdl-code

Description: filter-vhdl-code.rar为滤波器的完整VHDL程序，可用于IIR与FIR滤波器的仿真与验证实现，包括代码综合。使用版本为ISE6.3.-filter-vhdl-code.rar for the integrity of filter VHDL procedures, can be used for IIR and FIR filters realize simulation and verification, including an integrated code. Use version ISE6.3.
Platform: | Size: 173056 | Author: petri | Hits:

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