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[VHDL-FPGA-Verilog] 直流电机控制器

Description: 直流电机控制器，属于精品vhdl源码，可在eda仿真工具上仿真实现-DC motor controller is excellent VHDL source code can be sown in simulation tools Simulation
Platform: | Size: 2048 | Author: 阎磊 | Hits:

[VHDL-FPGA-Verilog] ddr_sdram_controller_vhdl

Description: ddr_sdram控制器的vhdl代码,里面的地址和数据长度可配置,能满足不同用户的需要.-ddr_sdram controller vhdl code, which addresses and the data length can be configured, meet the needs of different users.
Platform: | Size: 13312 | Author: hxwf801 | Hits:

[VHDL-FPGA-Verilog] MVHDL

Description: 本程式為並列flash ROM之控制程式, 可將flash rom的資料讀出後, 經過CPLD controller將圖檔轉成VESA影像訊號, 輸出至螢幕, 本程式已經過硬體驗證-the parallel program for controlling flash ROM programs, rom flash can be read out information, After drawing CPLD controller will turn into VESA video signal and output to screen. The program has strong experience card
Platform: | Size: 4977664 | Author: 明華 | Hits:

[Other] canvhdl

Description: can总线控制器的原代码，是用vhdl写的，我没有验证过，不保证正确性。可以作为参考。 -can Bus Controller's original code is written in vhdl, I have not tested, it does not guarantee accuracy. Can be used as reference.
Platform: | Size: 31744 | Author: 吴明诗 | Hits:

[VHDL-FPGA-Verilog] 8259

Description: 这是一个中断控制器的IP，功能很全，可以直接使用，类似于INTEL的8259，作为中断扩展。-This is an interrupt controller of the IP, is the whole function can be used directly, similar to INTEL in 8259, as extended interruption.
Platform: | Size: 2048 | Author: kristing | Hits:

[VHDL-FPGA-Verilog] elivator_control

Description: 电梯控制器 用于八层楼双电梯的协调调度 可进行扩展-Elevator controller for the eight-floor, two-elevator scheduling coordination can be extended
Platform: | Size: 544768 | Author: 王鹤 | Hits:

[VHDL-FPGA-Verilog] can_parts

Description: 实现CAN控制器的VHDL源码,与大家分享.-Realize CAN controller VHDL source code to share with you.
Platform: | Size: 40960 | Author: fhomewl | Hits:

[VHDL-FPGA-Verilog] can_rtl_verilog.tar

Description: can控制器的verilog语言实现 （还要更多的说明语言了吗？我不知道该写什么了）-controller can realize the Verilog language (even more language it? I do not know what the writing)
Platform: | Size: 34816 | Author: 郑国栋 | Hits:

[Other] VGALCD

Description: lcd控制器的源程序，可以随便使用，免费试用。不多描述。-lcd controller source code, you can not use, free trial. Not much to describe.
Platform: | Size: 494592 | Author: 刘源 | Hits:

[Other systems] elevator

Description: 电梯控制器 可实现电梯上下响应任务，到站提示音，无任务停在基站-Elevator controller can realize the lift up and down in response to mission departure and arrival tone, non-mission stopped at the base station
Platform: | Size: 1024 | Author: hilly | Hits:

[Other] sd_IP

Description: SD card controller can just read data using 1 bit SD mode. I have written this core for NIOS2 CPU, Cyclone, but I think it can works with other FPGA or CPLD. Better case for this core is SD clock = 20 MHz and CPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core. Good luck-SD card controller can just read data using 1 bit SD mode.I have written this core for NIOS2 CPU, Cyclone, but I think it can workswith other FPGA or CPLD. Better case for this core is SD clock = 20 MHz andCPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core.Good luck
Platform: | Size: 8192 | Author: tuya | Hits:

[VHDL-FPGA-Verilog] jiaotong

Description: 交通灯控制器的VHDL设计,能控制十字路口的红绿灯转换,通过目标芯片EPF10KLC84-4验证-Traffic lights controller VHDL design, can be controlled by traffic lights at the crossroads of the conversion, through the target chips EPF10KLC84-4 verification
Platform: | Size: 327680 | Author: ellala | Hits:

[VHDL-FPGA-Verilog] VHDL-SPI-Module.doc

Description: 本spi参数化通讯模块是一个支持SPI串行通信协议从协议的SPI从接口。可通过改变参数设置传输的位数，由外部控制器给定脉冲控制传输。-The parameters of spi communication module is a support SPI serial communication protocol from the agreement from the SPI interface. By changing the parameter settings can be transmitted over the median, given by an external controller to control transmission pulse.
Platform: | Size: 37888 | Author: | Hits:

[VHDL-FPGA-Verilog] can.tar

Description: can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases
Platform: | Size: 54272 | Author: yu | Hits:

[VHDL-FPGA-Verilog] CAN_IP

Description: 这是CAN总线控制器的IP核，源码是由Verilog HDL编写的。其硬件结构与SJA1000类似，满足CAN2.0B协议。-This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
Platform: | Size: 61440 | Author: 普林斯 | Hits:

[VHDL-FPGA-Verilog] canbus

Description: CAN通信协议的硬件描述语言代码，用于FPGA的总线接口控制器开发-CAN communication protocol of the hardware description language code for the FPGA bus interface controller development
Platform: | Size: 862208 | Author: shigengxin | Hits:

[VHDL-FPGA-Verilog] VHDL-dianti

Description: 高楼电梯自动控制系统(Windows平台上运行的ispLEVER编程软件。 ): 1统控制的电梯往返于1-9层楼。 2客要去的楼层数可手动输入并显示（设为A数）。 3梯运行的楼层数可自动显示（设为B数）。 4A>B时，系统能输出使三相电机正转的时序信号，使电梯上升； 当A<B时，系统能输出使三相电机反转的时序信号，使电梯下降； 当A=B时，系统能输出使三相电机停机的信号，使电梯停止运行并开门； 5是上升还是下降各层电梯门外应有指示，各层电梯门外应有使电梯上升或下降到乘客所在楼层的控制开关。 注：此为word文档，但里面有源代码。-High-rise elevator control system (Windows platform programming software running on the ispLEVER. ): An elevator control system and from 1-9 floors. 2, the number of passengers going to the floor can manually enter and display (Make A number). 3 ladder run automatically display the number of floors (Set B number). 4A> B, the system can output three-phase motor is transferred to the timing signal to lift up When A <B, the system can output three-phase motor to reverse the timing signal to the lift down When A = B, the system can output a signal to shut down three-phase motor, so that the lift stops and open the door 5 is increasing or decreasing the lift on each floor outside the door should be directed, due to lift on each floor outside the elevator up or down to the floor where the passenger control switch. Note: This is a word document, but inside the source code.
Platform: | Size: 34816 | Author: | Hits:

[VHDL-FPGA-Verilog] a-vhdl-can-controller

Description: a vhdl can controller project using vhdl programmming language-a vhdl can controller project using vhdl programmming language..
Platform: | Size: 112640 | Author: Rahul | Hits:

[VHDL-FPGA-Verilog] design-of-CAN-based-on-VHDL

Description: 基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计，实现其功能，并且能够在FPGA开发平台Quartos上通过仿真验证，证明其正确性-Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the CAN bus communication controller front-end design. Verilog HDL language that is used to complete the data link layer CAN protocol the RTL-level design, to achieve its function, and can be on the FPGA development platform Quartos by simulation to prove its correctness
Platform: | Size: 2615296 | Author: chen xinwei | Hits:

[SCM] a_vhdl_can_controller

Description: 使用VHDL语言，实现CAN控制器，支持CAN 2.0B(Use VHDL, realize CAN Controller, Support CAN 2.0B)
Platform: | Size: 409600 | Author: 飞雪漫天 | Hits:
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