Description: 适用于满足I2C协议的flash读/写操作程序,只需要设置要读/写的字节数,就可以直接使用!-Applicable to meet the I2C protocol flash read/write operations, only need to set to read/write number of bytes can be used directly! Platform: |
Size: 3072 |
Author:xiaoyuer |
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Description: Verilog HDL的程式,上網找到SPI程式,
vspi.v這程式相當好用可用來接收與傳送SPI,並且寫了一個傳輸信號測試,spidatasent.v這程式就是傳送的資料,分別為00 66... 01 77...... 02 55這樣的資料,並透過MAX+PULS II軟體進行模擬,而最外層的程式是test_createspi.v!-Verilog HDL programs, Internet find SPI program, vspi.v this very useful program can be used to receive and send SPI, and wrote a transmission signal test, spidatasent.v this program is to send the information, namely, 00 66 ... 01 77 ...... 02 55 This information, and through the MAX+ PULS II software simulation, while the outermost layer of the program are test_createspi.v! Platform: |
Size: 145408 |
Author:Rick |
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Description: I2C的ip核,Verilog实现,可以直接用在你的项目中。I2C是一种简单实用的通讯协议。-I2C' s ip nuclear, Verilog realization, you can directly use in your projects. I2C is a simple and practical protocol. Platform: |
Size: 2207744 |
Author:caibaiyin |
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Description: Verilog实现的I2C协议,直接在ISE下打开就可以-Verilog implementation I2C protocol to open directly in the ISE can be Platform: |
Size: 212992 |
Author:Roy |
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Description: FPGA控制SJA1000实现CAN协议 适合深入学子FPGA的学生 很不错-FPGA control the SJA1000 CAN protocol for in-depth realization of the students are very good students FPGA Platform: |
Size: 17577984 |
Author:qzl001 |
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Description: 用Verilog写的CAN协议IP核 已经验证可以使用 -CAN protocol written in Verilog IP core has been verified using Platform: |
Size: 1172480 |
Author:薛鹏举 |
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Description: I2C 控制器的 Verilog源程序以及I2C规范说明-The I2C bus provides a simple two-wire means of communication. This protocol is used in many applications.SDRAM modules implement a serial EEPROM that supports the I2C protocol. This is used so that a microproces-sor can read the EEPROM for confi guration purposes. Platform: |
Size: 9216 |
Author:zx |
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Description: 包含CAN协议讲解与CAN协议控制器的verilog实现(含有testbench),该实现模仿SJA1000架构,接口完全一致。压缩包中还包含SJA1000的手册与应用指南,非常好的CAN学习资料。-CAN protocol controller implemented in Verilog(contain testbench) & instruction of CAN protocol & datasheet and user manual of SJA1000 Platform: |
Size: 12809216 |
Author:zhangsong |
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Description: 购买的beckoff公司的ip核,提供了详细的datasheet以及协议说明,附上调用ip核的文件,采用verilog编写,平台可以在ISE里自己设置(Buy the beckoff company's ip kernel, provides a detailed datasheet and protocol description, attached to the ip kernel file, using verilog prepared, the platform can be set in the ISE itself) Platform: |
Size: 4682752 |
Author:cy白菜
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Description: 本设计是基于FPGA的高速并行接口通信接口和协议设计,该设计使用的是8
位并行接口,通过配置FPGA的FIFO寄存器保证了在高速并行下的数据稳定性,在 最终的测试中,该协议能够稳定传输的速度为80Mbps。(This design is based on FPGA high-speed parallel interface communication interface and protocol design, the design uses 8
Bit parallel interface ensures the data stability under high-speed parallel by configuring the FIFO register of FPGA. In the final test, the protocol can stably transmit at 80 Mbps.) Platform: |
Size: 19605504 |
Author:蔺娇娇 |
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