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[VHDL-FPGA-Verilog] CAN_IP

Description: 这是CAN总线控制器的IP核，源码是由Verilog HDL编写的。其硬件结构与SJA1000类似，满足CAN2.0B协议。-This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
Platform: | Size: 61440 | Author: 普林斯 | Hits:

[VHDL-FPGA-Verilog] Chapter-8

Description: Verilog编写的CAN通讯程序，通过验证，并支持CAN1.1,CAN2.0b协议。-CAN communication procedures written in Verilog, through validation, and support CAN1.1, CAN2.0b agreement.
Platform: | Size: 687104 | Author: 张跃平 | Hits:

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