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[VHDL-FPGA-Verilog] canbus

Description: CAN通信协议的硬件描述语言代码，用于FPGA的总线接口控制器开发-CAN communication protocol of the hardware description language code for the FPGA bus interface controller development
Platform: | Size: 862208 | Author: shigengxin | Hits:

[VHDL-FPGA-Verilog] canbus

Description: verilog 和VHDL实现的can总线接口代码-the realization of verilog and VHDL code of the can bus interface
Platform: | Size: 95232 | Author: bsyy | Hits:

[VHDL-FPGA-Verilog] canbus

Description: 用verilog编写实现的CAN总线控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the verilog source code to achieve the CAN bus controller, bring their own testbench, after decompression project file can be opened with the ISE.
Platform: | Size: 1079296 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] canbus

Description: CAN总线的FPGA实现，用Verilog编写，代码完整，而且有很完善的测试代码，用ISE直接打开，学习FPGA进阶的好项目-CAN Bus FPGA, written with Verilog, code integrity, but also very good test code, using ISE directly open, a good project to learn advanced FPGA
Platform: | Size: 863232 | Author: 张小琛 | Hits:

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