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[WEB Code] ripple-lookahead-carryselect-adder

Description: Ripple Adder: 16-bit 全加,半加及ripple adder的设计及VHDL程序 Carry Look ahead Adder:4, 16, 32 bits 前置进位加法器的设计方案及VHDL程序 Carry Select Adder:16 Bits 进位选择加法器的设计方案及VHDL程序-Ripple Adder : 16-bit full adder, semi-Canada and the ripple adder design and VHDL procedures Carry Look ahead Adder : 4, 16, 32 bits front rounding Adder and the VHDL design procedures Carry Select Adder : 16 Bits Progressive Choice Adder design and VHDL - sequence
Platform: | Size: 15972 | Author: 李成 | Hits:

[Firewall-Security] DCT域隐藏

Description: 当要隐藏信息时,在MATLAB的命令窗内输入命令: hide = myhide(carry,signal,x,y)； carry 用你的原始载体文件名代替，signal 用你所要隐藏的文件名代替 carry 和 signal 都必须是 *.* 的形式（注意不能省略单引号） x,y 是选取隐藏信息的位置坐标，在（x,y）和（y,x）处 生成的伪装载体文件名为hide.bmp 注意myhide.m文件，载体文件，隐藏文件都要在当前目录(current Directory)下 当要提取信息时，在MATLAB命令窗内输入命令： behidden = myinhide(carry,x,y)； carry 用你的伪装载体文件名代替,格式为 *.* （注意不要丢掉单引号） x,y 是选取隐藏信息的位置坐标，在（x,y）和（y,x）处，这必须和嵌入时所选位置一致。 提取出的信息文件名为behidden.bmp 同样，要注意behidden.m和伪装载体文件都要在当前目录(current Directory)下-when to hide information, in order MATLAB within a window orders : hide = myhide (carry, signal, x, y); Carry with you the original document name instead vector, signal used to hide your name in the paper and instead carry signal must be in the form of*.* ( not to single quotes omitted) x, y is to select the location of hidden information coordinates (x, y) and (y, x) The formation of camouflage vector document, entitled hide.bmp attention myhide.m documents, vector documents hidden all the documents in the current directory (current Directory) to retrieve information when, in order window MATLAB import order : behidden = myinhide (carry, x, y); carry using your camouflage vector file name instead, the format for*.* (take care not to lose a single quote) x, y election Hiding information
Platform: | Size: 203776 | Author: 韩飞 | Hits:

[Documents] ripple-lookahead-carryselect-adder

Description: Ripple Adder: 16-bit 全加,半加及ripple adder的设计及VHDL程序 Carry Look ahead Adder:4, 16, 32 bits 前置进位加法器的设计方案及VHDL程序 Carry Select Adder:16 Bits 进位选择加法器的设计方案及VHDL程序-Ripple Adder : 16-bit full adder, semi-Canada and the ripple adder design and VHDL procedures Carry Look ahead Adder : 4, 16, 32 bits front rounding Adder and the VHDL design procedures Carry Select Adder : 16 Bits Progressive Choice Adder design and VHDL- sequence
Platform: | Size: 15360 | Author: 李成 | Hits:

[VHDL-FPGA-Verilog] CSLA_32

Description: 32bit carry select adder
Platform: | Size: 1024 | Author: suha | Hits:

[VHDL-FPGA-Verilog] carrysel_adder_files

Description: This has code of carry select adder.. It is written in VHDL.. Hope its useful for beginners .. All the best-This has code of carry select adder.. It is written in VHDL.. Hope its useful for beginners .. All the best..
Platform: | Size: 2048 | Author: santhosh | Hits:

[Program doc] 5PG

Description: Design of High-Performance Low-Power Carry Select Adder using Dual Transition Skewed Logic (DTSL)I
Platform: | Size: 135168 | Author: Prabu | Hits:

[VHDL-FPGA-Verilog] p4_adder.tar

Description: 用vhdl实现的P4加法器，包括主要元件rca加法器，carry select adder,pg模块，并提供了一个测试文件，用modelsim测试通过-P4 adder implemented using VHDL, including the major component such as: rca adder, carry select adder, pg module,in addition provides a test file, all modules have been tested by modelsim
Platform: | Size: 3072 | Author: 胡恩 | Hits:

[VHDL-FPGA-Verilog] adder_csa

Description: carry select adder in verilog
Platform: | Size: 1024 | Author: Eric | Hits:

[VHDL-FPGA-Verilog] VHDL-ripple-lookahead-carryselect-adder

Description: vhdl code for ripple carry adder, carry select adder and carry look ahead adder
Platform: | Size: 17408 | Author: praveen | Hits:

[VHDL-FPGA-Verilog] adder_32bits

Description: 32位进位选择加法器，预置逻辑0和逻辑1，各模块并行运行，只要通过进位位选择逻辑0或者逻辑1即可，提高了运行速度。-32-bit carry select adder, preset logic 0 and logic 1, the modules run in parallel, as long as through the carry bit selection logic 0 or logic 1 can improve the speed.
Platform: | Size: 399360 | Author: JTEven | Hits:

[VHDL-FPGA-Verilog] 1.Area-Efficient-Carry-Select-Adder

Description: Area efficient carry save adder
Platform: | Size: 201728 | Author: arev | Hits:

[VHDL-FPGA-Verilog] Carry-Select-Adder

Description: verilog code for carry select adder
Platform: | Size: 47104 | Author: vishwabharath | Hits:

[Software Engineering] carry-select-adder

Description: Carry Select adder 32 bits in vhdl
Platform: | Size: 14336 | Author: | Hits:

[Software Engineering] carry-select-adder

Description: 进位选择加法器是一种比传统加法更快的加法器-Carry-select-adder is a new fast way to do the calculation
Platform: | Size: 1024 | Author: xiaodonghu | Hits:

[Other] Carry-select-Adder-4bit-Behavioral

Description: CARRY SELECT ADDER 4 BIT BAHAVIOURAL DESIGN
Platform: | Size: 1024 | Author: poths | Hits:

[Other] Carry-select-Adder-4bit-Dataflow

Description: CARRY SELECT ADDER 4 BIT DATAFLOW DESGIN
Platform: | Size: 1024 | Author: poths | Hits:

[Other] Carry-select-Adder-8bit-Dataflow

Description: CARRY SELECT ADDER 8 BIT DATAFLOW DESIGN
Platform: | Size: 2048 | Author: poths | Hits:

[Other] Area-Delay-Power-Efficient-Carry-Select-Adder-usi

Description: Implementation of IEEE 2015 paper for Area–Delay–Power Efficient Carry-Select Adder using VLSI verilog .The code tested by modelsim and also main program is test.v . If have any trouble mail to anandg.embedd@gmail.com-Implementation of IEEE 2015 paper for Area–Delay–Power Efficient Carry-Select Adder using VLSI verilog .The code tested by modelsim and also main program is test.v . If have any trouble mail to anandg.embedd@gmail.com
Platform: | Size: 610304 | Author: anandg | Hits:

[Other] carry select addr

Description: vhdl code for carry select adder
Platform: | Size: 9216 | Author: sajina | Hits:

[VHDL-FPGA-Verilog] 32-bit carry select adder verilog code

Description: 32-bit conventional carry select adder verilog code
Platform: | Size: 745 | Author: gsrwork2017@gmail.com | Hits:
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