Description: 介绍了carry_chain_adder，carry_skip_adder,ipple_carry_adder三种常用的加法器，采用verilogHDL语言，利用modelsim软件仿真验证，压缩包中包含有流程图-Introduced carry_chain_adder, carry_skip_adder, ipple_carry_adder three commonly used adder, using verilogHDL language, the use of ModelSim simulation software, compressed packet contains flowchart Platform: |
Size: 372736 |
Author:yaoyongshi |
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Description: The folder gives the 32 bit carry adder chain. IN CSA for cin = 1 or 0 ripple carry adders are used.-The folder gives the 32 bit carry adder chain. IN CSA for cin = 1 or 0 ripple carry adders are used. Platform: |
Size: 10240 |
Author:padmapriya |
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Description: 要求采用快速进位链（Look Ahead）设计一个21位加法器；
2) 采用结构化的设计方法，所有加法器均采用步骤1）的21位加法器；
3) 在加法器阵列中加入流水线结构（Pipelinc），输入连续送数，输出连续出结果，流水线填满后每拍输出一个结果；
-1) requires the use of fast carry chain (Look Ahead) design a 21-bit adder
2) the use of structured design methods, all adders are used in step 1) 21-bit adder
3) was added in the adder array pipeline structure (Pipelinc), enter the number of continuous feed, continuous output the results after each shot output lines to fill a result Platform: |
Size: 7168 |
Author:李少博 |
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