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[Other resource] crc_verilog_xilinx

Description: 这是一个在FPGA上实现CRC算法的程序，包含了CRC-8,CRC-12,CRC-16,CRC-CCIT,CRC-32一共五种校验形式。
Platform: | Size: 10591 | Author: 李奥运 | Hits:

[Crack Hack] crc

Description: CRC校验程序，使用了CRC-16和CRC-CCITT方法 -CRC inspection program, which use crc-16 and crc-ccitt method
Platform: | Size: 1024 | Author: 站长 | Hits:

[Embeded-SCM Develop] crc16

Description: A CCITT-16 CRC calculator. The source contains both the calculated (smaller but slower) version, and the table driven (faster but larger) version.
Platform: | Size: 3072 | Author: buaalzx | Hits:

[SCM] crc8

Description: 8051上的CRC8校验 A CCITT-8 CRC calculator. The source contains both the calculated (smaller but slower) version, and the table driven (faster but larger) version.-8051 CRC8 check on the CCITT A-8 CRC calculator. Th e source contains both the calculated (smaller but slower) version, and the table driven (faster but larger) versio n.
Platform: | Size: 2048 | Author: buaalzx | Hits:

[Mathimatics-Numerical algorithms] crc-ccitt

Description: CRC-CCITT码: G(x)=X16+X12+X5+1 多项式为 0x08408 用VC++写的DLL 用VB调用的 有调用实例 -CRC-CCITT code : G (x) = X16 X12 X5 to a polynomial with VC 0x08408 written with VB DLL called the Call example
Platform: | Size: 234496 | Author: 李慎丹 | Hits:

[SCM] CRC-CCITT-tab

Description: 一个生成反相CRC-CCITT校验码表的单片机C程序，反相CRC-CCITT＝ 0x8408,开发环境为Keil C51-a generation RP-CRC-CCITT CRC table of SCM C procedures, RP-CRC-CCITT = 0x8408, the development environment for Keil C51
Platform: | Size: 12288 | Author: 吴健 | Hits:

[Other Embeded program] crc

Description: 生成多项式的最高位必须是1。例如：CRC-CCITT标准的16位生成多项式：g（x）= x16+x12+x1+1；阶数r = 16 即：0x11021.最高位通常为1。-Generating polynomial must be the highest one. For example: CRC-CCITT standard 16-bit generation polynomial: g (x) = x16+ X12+ X1+ 1 order of r = 16 that is: 0x11021. Highest one usually.
Platform: | Size: 3072 | Author: xuhailun | Hits:

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: 这是一个在FPGA上实现CRC算法的程序，包含了CRC-8,CRC-12,CRC-16,CRC-CCIT,CRC-32一共五种校验形式。-err
Platform: | Size: 10240 | Author: 李奥运 | Hits:

[Voice Compress] crc

Description: CRC code for CCIT 16 CRC
Platform: | Size: 3072 | Author: ahsanhijazi | Hits:

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: 各类CRC效验码 有CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8-CONTAIN CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8
Platform: | Size: 6144 | Author: 吴伟珍 | Hits:

[VHDL-FPGA-Verilog] Perl_for_CRC

Description: Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8, CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32), any polynomial, and any data input width.-Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex ™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8 , CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32 ), any polynomial, and any data input width.
Platform: | Size: 90112 | Author: 尤恺元 | Hits:

[matlab] CRC_Check_sv2

Description: 运用matlab实现CRC编码。输入任意二进制数据，输出相应CRC编码。可选择CRC-12，CRC-16，CRC-CCIT 或者自己输入多项式系数。-CRC coding using matlab realize. Arbitrary binary data input, the output corresponding CRC encoding. Optional CRC-12, CRC-16, CRC-CCIT or enter your own polynomial coefficients.
Platform: | Size: 7168 | Author: 刘蛋蛋 | Hits:

[VHDL-FPGA-Verilog] CRC

Description: CRC校验参考设计Verilog代码,crc8,16,32bit- crc8_8.v : CRC-8, 8-bit data input. crc12_4.v : CRC-12, 4-bit data input. crc16_8.v : CRC-16, 8-bit data input. crc_ccit_8.v : CRC-CCIT, 8-bit data input. crc32_8.v : CRC-32, 8-bit data input.
Platform: | Size: 10240 | Author: guangngqiang | Hits:

[Other] CRC_CCIT_Sim

Description: RS232的发送带CRC-CCIT校验,适合CRC初学者-CRC-CCIT_Sim for Rs232 Tx， for new student of CRC by FPGA
Platform: | Size: 6144 | Author: 小付 | Hits:

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: 包括下面文档： readme.txt : This file crc8_8.v : CRC-8, 8-bit data input. crc12_4.v : CRC-12, 4-bit data input. crc16_8.v : CRC-16, 8-bit data input. crc_ccit_8.v : CRC-CCIT, 8-bit data input. crc32_8.v : CRC-32, 8-bit data input. crcgen.pl : Perl script used to generate Verilog Source for CRC caluculation.(Contains the following files readme.txt : This file crc8_8.v : CRC-8, 8-bit data input. crc12_4.v : CRC-12, 4-bit data input. crc16_8.v : CRC-16, 8-bit data input. crc_ccit_8.v : CRC-CCIT, 8-bit data input. crc32_8.v : CRC-32, 8-bit data input. crcgen.pl : Perl script used to generate Verilog Source for CRC caluculation.)
Platform: | Size: 10240 | Author: chris_lj | Hits:

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