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[Other resourcecic_filter

Description: CIC滤波器的matlab设计文件,对于实际的电路参考价值很大
Platform: | Size: 1605 | Author: ylt | Hits:

[Other resourcecic_filter

Description: 关于软件无线电中CIC滤波器的实现与仿真
Platform: | Size: 1605 | Author: 林恩 | Hits:

[CSharpCIC_filter

Description: CIC_filter
Platform: | Size: 4327 | Author: koko3ko333 | Hits:

[matlabcic_filter

Description: CIC滤波器的matlab设计文件,对于实际的电路参考价值很大-CIC filter matlab design documents, the actual circuit for a great reference value
Platform: | Size: 1024 | Author: ylt | Hits:

[matlabcic_filter

Description: 关于软件无线电中CIC滤波器的实现与仿真-On Software Radio CIC Filter Implementation and Simulation
Platform: | Size: 2048 | Author: 林恩 | Hits:

[Communication-MobileCIC_FILTER

Description: 详细介绍了在软件无线电中广泛采用的变速率滤波器-CIC滤波器的原理及实现方法-Described in detail in the software radio is widely used in variable-rate filter-CIC filter and the implementation of the principle
Platform: | Size: 143360 | Author: yeping | Hits:

[VHDL-FPGA-VerilogCIC_filter

Description: CIC滤波器的原理及FPGA实现 里面有我收集的各种关于CIC滤波器的FPGA 实现的文章及源码-CIC filter FPGA realization of the principle and there are a variety of my collection on the CIC filter FPGA implementation and the source article
Platform: | Size: 1709056 | Author: 应清 | Hits:

[VHDL-FPGA-Verilogcic_filter

Description: 5阶cic滤波器 使用vdhl编写 下载后将tb代码烤出 新建,然后综合仿真!-5 cic filter using vdhl written order to download the code will tb baked New, and then integrated simulation!
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-VerilogCIC_filter

Description: 三级级联梳状滤波器(CIC)的verilog实现。顶层模块top_moduole下面包含三个子模块,积分模块integrated,抽取模块decimate和梳状滤波器模块comb,已验证可综合通过并实现CIC功能-Three-level cascade comb filter (CIC) verilog implementation.Top-level module top_moduole below contains three child module, integral module integrated, extraction module decimate and comb comb filter module, verified and can be integrated by CIC functions
Platform: | Size: 2048 | Author: xuzigeng | Hits:

[ConsoleCIC_filter

Description: CIC filter improved. For communication engineers , this is very important to learn and apply for practical system realization. We have done some changes in previous available codes and enhanced the performance.-CIC filter improved. For communication engineers , this is very important to learn and apply for practical system realization. We have done some changes in previous available codes and enhanced the performance.
Platform: | Size: 1024 | Author: waqar | Hits:

[VHDL-FPGA-VerilogCIC_filter

Description: 抽取:(接收端) 中频信号IF 20M(采样率是50M) 下变频信号 MIX_O 1M(50M) 采用CIC滤波器进行降采样率。 插值:(发送端) 基带信号上变频到1M,采样率是2.5M,采用CIC滤波器进行升采样率处理。 注释:升采样率或者降采样率不会改变原始信号的中心频率,但是频谱分布会发生改变。-Extraction: (receiver) IF signal 20M (sampling rate is 50M) down-conversion signal MIX_O 1M (50M) using CIC filter down sampling rate. Interpolation: (sending side) Baseband signal up to 1M, the sampling rate is 2.5M, using CIC filter for sampling rate processing. Note: The up-sampling rate or down-sampling rate does not change the center frequency of the original signal, but the spectral distribution will change.
Platform: | Size: 9699328 | Author: 曾锦 | Hits:

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