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[VHDL-FPGA-Verilog] CORDIC01

Description: CORDIC算法的硬件实现 用的verilog语言-CORDIC algorithm Hardware Implementation of the Verilog language
Platform: | Size: 221184 | Author: 李文文 | Hits:

[VHDL-FPGA-Verilog] adder_ahead8bit

Description: 本文件提供了用verilog HDL语言实现的8位超前进位加法器,充分说明了超前进位加法器和普通加法器之间的区别.-using verilog HDL achieve the eight-ahead adder, fully demonstrates the CLA for ordinary Adder and the distinction between.
Platform: | Size: 10240 | Author: 剑指眉梢 | Hits:

[MPI] adder

Description: 8位超前进位加法器 就是使各位的进位直接由加数和被加数来决定，而不需要依赖低位进位-8-bit CLA is to make your binary direct summand by summand and to decide, rather than to rely on low binary
Platform: | Size: 7168 | Author: | Hits:

[VHDL-FPGA-Verilog] add2

Description: 两个4bit超前进位加法器实现8bit加法器-Two 4bit CLA realize 8bit adder
Platform: | Size: 152576 | Author: 徐芬 | Hits:

[VHDL-FPGA-Verilog] 16bitCLA

Description: 基于Verilog HDL的16位超前进位加法器 分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules
Platform: | Size: 7168 | Author: 韩伟 | Hits:

[Windows Develop] 128bitCLA

Description: 128位CLA 采用kogge-stone tree算法 经modlesim验证正确-128-bit CLA using kogge-stone tree algorithm as the right to verify modlesim
Platform: | Size: 1024 | Author: 韩伟 | Hits:

[MPI] adder

Description: 运用VHDL语言实现四位超前进位加法器。-VHDL language using the four CLA.
Platform: | Size: 4096 | Author: 吴伟 | Hits:

[Other] adder17

Description: 实现17位加法，利用一个16位超前进位加法器和一个一位全加器构成的一个有进位输入和进位输出的17加法器，并且16位加法器利用的使四位超前进位加法器构成。它在booth乘法器设计中经常用到。可以使初学者对模块的调用了解更加透彻。-Adder 17 to achieve the use of a 16-bit CLA, and a one-bit full adder composed of a binary input and binary output of the adder 17, and 16-bit adder to make use of four CLA pose. Multiplier in the booth design frequently used. Modules will enable beginners to a more thorough understanding of the call.
Platform: | Size: 2048 | Author: htpq | Hits:

[VHDL-FPGA-Verilog] CLA.VHDL.CODE

Description: cla vhdl code with a picture files.
Platform: | Size: 339968 | Author: YD | Hits:

[VHDL-FPGA-Verilog] ADDER(2)

Description: simple 16-bet CLA adder
Platform: | Size: 2048 | Author: calvin | Hits:

[Windows Develop] adder

Description: 8位cla，采用for结构，可以扩张成32位或者16位-8 cla, used for the structure, you can expand into a 32-bit or 16-bit
Platform: | Size: 36864 | Author: sigma | Hits:

[Software Engineering] cla

Description: Carry Look ahead adder
Platform: | Size: 2048 | Author: Senthil Kumar | Hits:

[Books] VHDL

Description: A gate level implementation of a Booth Encoded Radix-4 24 bit multiplier with VHDL code in structural form. Carry-save adder and hierarchical CLA adder is used for the component adders in the design. The 12 partial products is a Wallace Adder Tree built from Carry-save adder using 3 to 2 reduction. A hierarchical CLA ( Carry-look-Ahead Adder ) adder is used for the final product generation. -A gate level implementation of a Booth Encoded Radix-4 24 bit multiplier with VHDL code in structural form. Carry-save adder and hierarchical CLA adder is used for the component adders in the design. The 12 partial products is a Wallace Adder Tree built from Carry-save adder using 3 to 2 reduction. A hierarchical CLA ( Carry-look-Ahead Adder ) adder is used for the final product generation.
Platform: | Size: 7168 | Author: Michael Lee | Hits:

[matlab] 16bit-CLA

Description: a 16 bit carry look ahead adder verilog code
Platform: | Size: 8192 | Author: praveen | Hits:

[VHDL-FPGA-Verilog] CLA

Description: carry look ahead adder
Platform: | Size: 31744 | Author: nikost87 | Hits:

[VHDL-FPGA-Verilog] 16bit-CLA

Description: 16 bit carry look ahead adder verilog code
Platform: | Size: 8192 | Author: praveen | Hits:

[VHDL-FPGA-Verilog] cla-adder

Description: cla adder code in vhdl
Platform: | Size: 8192 | Author: nirjhar | Hits:

[assembly language] 32-bit-cla-adder

Description: This a code that describe 32 bit carry look ahead adder in VHDL(32 bit CLA).-This is a code that describe 32 bit carry look ahead adder in VHDL(32 bit CLA).
Platform: | Size: 1024 | Author: hskim | Hits:

[Other] CLA

Description: CLA adder:use vhdl to write the carry-lookahead adder which is a type of adder used in digital logic-CLA adder
Platform: | Size: 1024 | Author: awen | Hits:

[Other] cla

Description: CLA A dder Generator CLA A dde r Gen erator CLA Adder Gene ra t or CLA Adder Gen er ator
Platform: | Size: 4096 | Author: Sreeraj R | Hits:
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