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[Other resource] my_design_frequency

Description: 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号是最重要的信号之一。 下面我们介绍分频器的 VHDL 描述，在源代码中完成对时钟信号 CLK 的 2 分频， 4 分频， 8 分频， 16 分频。 这也是最简单的分频电路，只需要一个计数器即可。-in digital circuits, and often the need for higher frequency for the clock frequency operation, the lower frequency clock signal. We know that the hardware circuit design clock signal is the most important one of the signals. Below us Divider VHDL description of the source code for the completion of the clock signal CLK frequency of 2 hours, 4 frequency, frequency of 8 hours, 16 minutes frequency. This is the most simple-frequency circuit, only one counter will be.
Platform: | Size: 1435 | Author: 卢吉恩 | Hits:

[Other resource] clk-div

Description: VHDL code for a clock divider by 27 circuit with a resulting waveform with 50％ duty cycle..
Platform: | Size: 3035 | Author: 李军 | Hits:

[RFID] dpll

Description: DPLL由 鉴相器 模K加减计数器 脉冲加减电路 同步建立侦察电路 模N分频器 构成. 整个系统的中心频率(即signal_in和signal_out的码速率的2倍) 为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低.-DPLL phase detector by the addition and subtraction counter modulus K synchronous pulse addition and subtraction circuit detection circuit establishing mode N divider constituted. The entire system of the center frequency (ie signal_in and signal_out the code rate of 2 times) for clk/8/N. Modulus K addition and subtraction of the K value of Counter DPLL decision accuracy and synchronization set-up time, K the greater the synchronization set-up time is long, synchronous and high accuracy. In contrast the short and low.
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] clk-div

Description: VHDL code for a clock divider by 27 circuit with a resulting waveform with 50％ duty cycle..
Platform: | Size: 3072 | Author: 李军 | Hits:

[VHDL-FPGA-Verilog] FPQ

Description: 分频器的vhdl描述，在源代码中完成对时钟信号CLK的2分频,4分频,8分频,16分频-Divider vhdl description of the source code at the completion of the CLK clock signal frequency of 2 hours, 4 minutes frequency, frequency of 8 hours, 16 minutes frequency
Platform: | Size: 1024 | Author: LS | Hits:

[Windows Develop] DVF

Description: 数控分频器的设计数控分频器 端口定义： CLK：时钟输入 D[7..0]：预置数据 Fout：分频输出 说明： D[7..0]作为8位加1计数器的初值，初值越大，分频输出频率越高，反之越低， -NC NC divider divider port the definition of design: CLK: Clock input D [7 .. 0]: preset data Fout: frequency output that: D [7 .. 0] as 8-bit counter plus 1 the initial value, the greater the initial value, the higher the output frequency divider, on the contrary the lower the
Platform: | Size: 1024 | Author: 张娟 | Hits:

[Com Port] 9600divider

Description: 任意分频器,可以实现FPGA的CLK分频功能，已通过编译-Arbitrary frequency divider can be achieved FPGA-CLK sub-band capabilities, has passed the compilation
Platform: | Size: 195584 | Author: liujieyu | Hits:

[VHDL-FPGA-Verilog] clk_divider

Description: Simple Clk Divider for FPGA design in Verilog -Simple Clk Divider for FPGA design in Verilog
Platform: | Size: 1024 | Author: h_j_tel | Hits:

[MPI] clk

Description: 二分之一分频器及其测试程序，是用modelsim仿真实现-One half of the divider and the test procedure is used modelsim Simulation
Platform: | Size: 1024 | Author: 张依 | Hits:

[VHDL-FPGA-Verilog] The-use-of-VHDL-divider-design

Description: 分频器的各种设计方法， 及源代码，源代码中完成对时钟信号CLK的2分频，4分频，8分频，16分频。-The use of VHDL divider design
Platform: | Size: 5120 | Author: 王子冉 | Hits:

[Linux-Unix] clk-fixed-factor

Description: basic fixed multiplier and divider clock that cannot gate.
Platform: | Size: 1024 | Author: jdfzws | Hits:

[Linux-Unix] clk-imx6q

Description: The multiplexer and divider of imx6q clock gpu3d_shader get redefined reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl. -The multiplexer and divider of imx6q clock gpu3d_shader get redefined reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl.
Platform: | Size: 6144 | Author: terneng998 | Hits:

[Linux-Unix] clk-ls1x

Description: imx integer fixup divider clock for Linux v2.13.6.
Platform: | Size: 2048 | Author: ginkengvv | Hits:

[Linux-Unix] clk-divider

Description: Frontend part of the Linux driver for the Afatech 9005 USB1.1 DVB-T receiver.
Platform: | Size: 9216 | Author: kinyaivw | Hits:

[Linux-Unix] clk-corediv

Description: MVEBU Core divider clock.CORE_CLK_DIV_RATIO_MASK.
Platform: | Size: 2048 | Author: boubthi | Hits:

[Linux-Unix] clk-frac

Description: The clock is an adjustable fractional divider with a busy bit to wait when the divider is adjusted.
Platform: | Size: 1024 | Author: nanvieba | Hits:

[Linux-Unix] clk-divider

Description: linux sound pxa2xx-ac97.c AC97 support for the Intel PXA2xx chip. -linux sound pxa2xx-ac97.c AC97 support for the Intel PXA2xx chip.
Platform: | Size: 4096 | Author: wieksding | Hits:

[Linux-Unix] clk

Description: This fixups the register CCM_CSCMR1 write value. The write read divider values of the aclk_podf field of that register have the relationship described by the following table:.
Platform: | Size: 2048 | Author: xdpangsj | Hits:

[VHDL-FPGA-Verilog] clk-divide5

Description: 实现5分频计数的veriog电路，简单易懂，欢迎大家下载学习-Achieve 5 divider count veriog circuit, easy to understand, welcome to download the study
Platform: | Size: 1024 | Author: 李佳旭 | Hits:

[Other] vhdl_time

Description: it is a clk divider
Platform: | Size: 3072 | Author: immu1 | Hits:
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