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[Other resource] my_design_frequency

Description: 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号是最重要的信号之一。 下面我们介绍分频器的 VHDL 描述，在源代码中完成对时钟信号 CLK 的 2 分频， 4 分频， 8 分频， 16 分频。 这也是最简单的分频电路，只需要一个计数器即可。-in digital circuits, and often the need for higher frequency for the clock frequency operation, the lower frequency clock signal. We know that the hardware circuit design clock signal is the most important one of the signals. Below us Divider VHDL description of the source code for the completion of the clock signal CLK frequency of 2 hours, 4 frequency, frequency of 8 hours, 16 minutes frequency. This is the most simple-frequency circuit, only one counter will be.
Platform: | Size: 1435 | Author: 卢吉恩 | Hits:

[Other resource] clk-div

Description: VHDL code for a clock divider by 27 circuit with a resulting waveform with 50％ duty cycle..
Platform: | Size: 3035 | Author: 李军 | Hits:

[VHDL-FPGA-Verilog] my_design_frequency

Description:
Platform: | Size: 1024 | Author: 卢吉恩 | Hits:

[VHDL-FPGA-Verilog] divide

Description: 除法器的设计本文所采用的除法原理是：对于八位无符号被除数A，先对A转换成高八位是0低八位是A的数C，在时钟脉冲的每个上升沿C 向左移动一位，最后一位补零，同时判断C的高八位是否大于除数B，如是则C的高八位减去B，同时进行移位操作，将C的第二位置1。否则，继续移位操作。经过八个周期后，所得到的C的高八位为余数，第八位为商。从图(1)可清楚地看出此除法器的工作原理。此除法器主要包括比较器、减法器、移位器、控制器等模块。-Divider design used in this paper, the principle of division is: For the eight unsigned dividend A, the first of A into the high-low 8 0 8 is the A number of C, in each clock rising edge to the left C Mobile One, and finally a zero, at the same time to determine whether C is greater than the high-8 divisor B, so is the high C 8 minus B, at the same time shift operation, the location will be C s second one. Otherwise, continue to shift operation. After eight cycles, received a high C for more than eight the number of eighth place for the business. From Figure (1) can clearly see that the divider works. This mainly includes divider comparators, subtraction, and shifter, controller modules.
Platform: | Size: 1024 | Author: lyy | Hits:

[VHDL-FPGA-Verilog] clk-div

Description: VHDL code for a clock divider by 27 circuit with a resulting waveform with 50％ duty cycle..
Platform: | Size: 3072 | Author: 李军 | Hits:

[VHDL-FPGA-Verilog] FPQ

Description: 分频器的vhdl描述，在源代码中完成对时钟信号CLK的2分频,4分频,8分频,16分频-Divider vhdl description of the source code at the completion of the CLK clock signal frequency of 2 hours, 4 minutes frequency, frequency of 8 hours, 16 minutes frequency
Platform: | Size: 1024 | Author: LS | Hits:

[VHDL-FPGA-Verilog] clock_divider

Description: This code contains the simple program that can be used for the clock divider to set any desireable clock from the master clock.
Platform: | Size: 1024 | Author: Shahzad | Hits:

[VHDL-FPGA-Verilog] clk_div

Description: Thia is VHDL code for clock divider
Platform: | Size: 49152 | Author: Marija | Hits:

[VHDL-FPGA-Verilog] divider

Description: a clock divider vhdl code
Platform: | Size: 236544 | Author: mansih | Hits:

[VHDL-FPGA-Verilog] clock-divider

Description: VHDL code for clock divider circuit. There are two modules: one output divide by 4 and other outputs divide by 6
Platform: | Size: 1024 | Author: zpatel | Hits:

[VHDL-FPGA-Verilog] Package

Description: Package consists of two pdf files: i)cdr project: theory and implementation of vhdl ii)I2C bus controller: xilinx implementation of uC interface on CPLD Package consists of 7 vhdl files: string_detector: detects the continuous string of 111 led_driver: code for running leds on dvpt board clk_div: clock divider circuitry (component for led code) mem: memory component for led code ram_dual: dual port ram implementation-Package consists of two pdf files: i)cdr project: theory and implementation of vhdl ii)I2C bus controller: xilinx implementation of uC interface on CPLD Package consists of 7 vhdl files: string_detector: detects the continuous string of 111 led_driver: code for running leds on dvpt board clk_div: clock divider circuitry (component for led code) mem: memory component for led code ram_dual: dual port ram implementation
Platform: | Size: 4604928 | Author: Sharav | Hits:

[VHDL-FPGA-Verilog] VHDL-counter

Description: 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号时非常重要的。 下面我们介绍分频器的VHDL描述，在源代码中完成对时钟信号CLK的2分频，4分频，8分频，16分频。 -In digital circuits, and often need high frequency clock divider operating in lower frequency clock signal. We know that when the clock signal in the hardware circuit design is very important. Here we introduce the VHDL description of the divider in the source code of the clock signal CLK divided by 2, 4 divider, divide by 8, divided by 16.
Platform: | Size: 86016 | Author: zhanghua | Hits:

[VHDL-FPGA-Verilog] clock-divider

Description: clock generator vhdl code
Platform: | Size: 1024 | Author: sgma | Hits:

[VHDL-FPGA-Verilog] shumaguandongtai

Description: VHDL的动态扫描显示六个数码管，包含分频代码产生25kHz的扫描信号作为时钟。-VHDL dynamic scanning display six digital tube contains 25kHz scanning signal is generated as a clock divider code.
Platform: | Size: 564224 | Author: DW | Hits:

[Windows Develop] clock1

Description: 该代码实现的是使用VHDL语言编程实现的FPGA上的时钟分频。通过修改代码中的参数改变FPGA的输出时钟频率。-The code implements the VHDL language programming on the FPGA clock divider. Changed by modifying the parameters in the code of the output clock frequency of the FPGA.
Platform: | Size: 3146752 | Author: 赵晨楠 | Hits:

[File Format] Dll-Files

Description: clock divider code for vhdl
Platform: | Size: 8444928 | Author: asdasd | Hits:

[Other] clkNdiv

Description: 很经典的时钟分频代码，直接拿来可以使用 使用VHDL语言编写！-Very classic clock divider code can be directly used to use using VHDL language!
Platform: | Size: 20480 | Author: 杨遥 | Hits:

[VHDL-FPGA-Verilog] Clockdivider

Description: VHDL CODE FOR CLOCK DIVIDER
Platform: | Size: 859136 | Author: pinky | Hits:

[VHDL-FPGA-Verilog] Divider

Description: VHDL代码实现分频器设计 分频器系统时钟20万分频 上升沿触发-VHDL code Divider Design The system clock frequency divider 20 extremely Rising edge triggered
Platform: | Size: 2048 | Author: 123456789 | Hits:

[DSP program] code

Description: vhdl code which includes various codes of clock divider uart lcd etc
Platform: | Size: 2028544 | Author: devi | Hits:
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