Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - clock_vhdl

Search list

[Other resource] clock_VHDL

Description: VHDL设计的数字时钟，有闹钟、整点报时等功能
Platform: | Size: 510989 | Author: 王毅诚 | Hits:

[Other resource] clock_VHDl

Description: 一个初学者写的时钟程序，VHDL语言，MAXPLUS环境。
Platform: | Size: 6247 | Author: 朱涛 | Hits:

[Other systems] clock_VHDL

Description: VHDL设计的数字时钟，有闹钟、整点报时等功能-VHDL design of the digital clock has an alarm clock, the whole point timekeeping functions
Platform: | Size: 510976 | Author: 王毅诚 | Hits:

[VHDL-FPGA-Verilog] clock_VHDl

Description: 一个初学者写的时钟程序，VHDL语言，MAXPLUS环境。-The clock to write a beginners program, VHDL language, MAXPLUS environment.
Platform: | Size: 6144 | Author: 朱涛 | Hits:

[VHDL-FPGA-Verilog] clock_VHDL

Description: 主要供学习FPGA的人员学习如何写VHDL程序之用，该程序实现了时钟的二分频等功能。-Primarily for learning FPGA-VHDL program to learn how to write use, the program achieved the second clock frequency and so on.
Platform: | Size: 1041408 | Author: cao | Hits:

[VHDL-FPGA-Verilog] clock_vhdl

Description: 使用quartus ii开发的FPGA电子时钟的VHDL源代码，分模块写法，在1602液晶上显示，具有走时，调节时间功能-Using quartus ii the development of electronic clock FPGA VHDL source code, sub-module written in the 1602 LCD display, with travel time, settling time function
Platform: | Size: 617472 | Author: 陈飞 | Hits:

[VHDL-FPGA-Verilog] digital-clock_VHDL

Description: 使用VHDL实现数字时钟，已在FPGA上验证-use VHDL to build a digital clock, has been validated on FPGA
Platform: | Size: 5120 | Author: tufengbin | Hits:

CodeBus www.codebus.net