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[Editor] cnt10

Description: 用VHDL语言编的带有异步清零功能的十进制计数器-using VHDL addendum to the asynchronous reset function with the decimal counter
Platform: | Size: 30560 | Author: yanyuntao | Hits:

[Other resource] cnt10

Description: 基于vhdl的10进制计数器模块，实现0-9计数
Platform: | Size: 24101 | Author: 贝凯 | Hits:

[Other resource] testctl

Description: 本程序实现了一个数字频率计。它由一个测频控制信号发生器TESTCTL，8个有时钟的十进制计数器CNT10，一个32位锁存器REG32B组成。
Platform: | Size: 1130 | Author: liushenshen | Hits:

[Other resource] cnt10

Description: led 跑马灯，8个led灯采用cnt10位计数器计数跑马
Platform: | Size: 165636 | Author: yyqdian | Hits:

[Other resource] cnt10

Description: 10进制计数器，VHDL描述的，实验必备
Platform: | Size: 45923 | Author: li | Hits:

[Editor] cnt10

Description: 用VHDL语言编的带有异步清零功能的十进制计数器-using VHDL addendum to the asynchronous reset function with the decimal counter
Platform: | Size: 30720 | Author: yanyuntao | Hits:

[VHDL-FPGA-Verilog] cnt10

Description: 基于vhdl的10进制计数器模块，实现0-9计数-VHDL-based 10-band counter module, to achieve 0-9 count
Platform: | Size: 23552 | Author: 贝凯 | Hits:

Description: 本程序实现了一个数字频率计。它由一个测频控制信号发生器TESTCTL，8个有时钟的十进制计数器CNT10，一个32位锁存器REG32B组成。-This procedure implements a digital frequency meter. It consists of a frequency control signal generator TESTCTL, 8 which have the metric system clock counter CNT10, a 32-bit latch REG32B component.
Platform: | Size: 1024 | Author: liushenshen | Hits:

[SCM] cnt10

Description: led 跑马灯，8个led灯采用cnt10位计数器计数跑马-Marquee led, led lamp using 8-bit counter counts cnt10 Happy Valley
Platform: | Size: 164864 | Author: yyqdian | Hits:

[VHDL-FPGA-Verilog] cnt10

Description: 10进制计数器，VHDL描述的，实验必备-10 hexadecimal counters, VHDL description of the experiment must
Platform: | Size: 46080 | Author: li | Hits:

[VHDL-FPGA-Verilog] pinluji

Description: 四位十进制频率计设计包含测频控制器（TESTCTL），4位锁存器(REG4B)，十进制计数器（CNT10）的原程序(vhd)，波形文件(wmf ),包装后的元件(bsf)。顶层原理图文件（Block1.bdf）和波形。 -Four decimal frequency meter measuring frequency controller design includes (TESTCTL), 4 bit latch (REG4B), decimal counter (CNT10) of the original procedure (vhd), waveform file (wmf), packaged components (bsf). Top-level schematic document (Block1.bdf) and waveform.
Platform: | Size: 11264 | Author: 深空 | Hits:

[Windows Develop] cnt10

Description: 含异步清0和同步时钟使能的加法计数器，可以通过时钟源的选择，实现不同速度的输出。-With asynchronous and synchronous clock-ching 0 enabled adder counter, clock source can be the choice of different speeds to achieve the output.
Platform: | Size: 131072 | Author: weigong | Hits:

[Windows Develop] CNT10

Description: 这是十进制计数器的源程序，有需要的同学可以参照一下！-This is the decimal counter source, needy students can refer to you!
Platform: | Size: 35840 | Author: 逗号 | Hits:

[VHDL-FPGA-Verilog] pinlvji

Description: 用4位十进制计数器对用户输入时钟信号进行计数，计数间隔为1秒钟。计数满1秒钟后将计数值（即频率值）所存到4位寄存器中显示，并将计数器清0，在进行下一次计数。频率计由三种模块组成：testctl为控制模块，由1Hz其准产生rst_cnt,load,cnt_en信号；cnt10为带清0及计数允许的十进制计数器；reg4b为四位寄存器。 -With four decimal counter input clock signal to the user to count, count one second interval. 1 seconds after the full count of values (that is, the frequency value) stored in the register to display 4, and Counter-ching 0, the time of the next count. Frequency of three modules: testctl for the control module, the alignment of 1Hz generated by rst_cnt, load, cnt_en signal cnt10 with clearance for the count 0 and the decimal counter permit reg4b register for the four.
Platform: | Size: 10841088 | Author: 袁玉佳 | Hits:

[VHDL-FPGA-Verilog] cnt10

Description: vhdl 十进制加法计数器设计已经调试成功-decimal adder vhdl counter the success of design debugging
Platform: | Size: 27648 | Author: 程诗宇 | Hits:

[VHDL-FPGA-Verilog] CNT10-START

Description: 十进制计数器的设计的源代码 verilog语言 -conter10
Platform: | Size: 1108992 | Author: 于慧敏 | Hits:

[VHDL-FPGA-Verilog] cnt10

Description: 一个用VHDL语言编写的十进制计数器，后续还有分频器、数据选择器、七段数码显示程序等软件平台是Quartus II 7.2 ，最后通过这些小的模块可以组合起来制作出一个时钟或者其它的任意进制计数器，适合初学者，通过这些程序，刚接触VHDL的学习者可以一步步的去认识和了解VHDL，最后通过设计一个具有实用功能的电路，来增加学习者的成就感和学习兴趣。所有程序软硬件调试都成功通过，硬件平台是自己学校设计的一块开发板，要了解的可以联系本人。联系QQ：782649157 -VHDL language using a decimal counter, follow-up there is divider, data selector, seven-segment digital display procedures, the software platform is Quartus II 7.2, the final adoption of these small modules can be combined to produce a clock or other arbitrary binary counter, suitable for beginners, through these procedures, new to VHDL learners can be a step by step to the awareness and understanding of VHDL, the last through the design of a practical function of the circuit, to increase the learner' s sense of achievement and interest in learning. All programs have successfully passed the hardware and software debugging, hardware platform is designed by a development of their own school board, it is necessary to know can contact me. Contact QQ: 782649157
Platform: | Size: 242688 | Author: QQ | Hits:

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[Editor] cnt10

[Other resource] cnt10

[Other resource] testctl

[Other resource] cnt10

[Other resource] cnt10

[Editor] cnt10

[VHDL-FPGA-Verilog] cnt10

[SCM] testctl

[SCM] cnt10

[VHDL-FPGA-Verilog] cnt10

[VHDL-FPGA-Verilog] pinluji

[Windows Develop] cnt10

[Windows Develop] CNT10

[VHDL-FPGA-Verilog] pinlvji

[VHDL-FPGA-Verilog] cnt10

[VHDL-FPGA-Verilog] CNT10-START

[VHDL-FPGA-Verilog] cnt10

[VHDL-FPGA-Verilog] cnt10

[VHDL-FPGA-Verilog] CNT10

[VHDL-FPGA-Verilog] cnt10

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