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[VHDL-FPGA-Verilog] OR1200_verilog DL : 0: or1200开源risc cpu的verilog描述实现，cpu源代码分析与芯片设计一书的源码-or1200 open source Verilog description of the risc cpu realize, cpu source code analysis and chip design source book
Update : 2025-03-11 Size : 200kb Publisher : yu