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[
VHDL-FPGA-Verilog
]
frame_sync
Description:
帧同步模块的Veriolog源码。 在ModelSim下的一个工程。有测试文件。-frame synchronization module Veriolog source. The ModelSim of a project. A test document.
Platform:
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Size:
24576
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Author:
刘仪
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Search - code vhd dvb