Location:
Search - coprocessor a
Search list
Description: The paper presents the CORDIC Algorithm, which has been implemented as an virtual component (IP core) in a VHDL simulation environment. The core is packaged as a soft (VHDL) macro and it implements all transcenden-tal functions. Analysis of the accuracy of the algorithms implemented shows that the CORDIC functions are equivalent to the accuracy of a Pentium coprocessor.
Platform: |
Size: 117831 |
Author: 赵平 |
Hits:
Description: RK3066 DATASHEET. RK3066 is a low power, high performance processor solution for mobile phones, personal mobile internet device and other digital multimedia applications, and integrates dual-core Cortex-A9 with separately NEON and FPU coprocessor
Platform: |
Size: 806399 |
Author: hi366@126.com |
Hits:
Description: The paper presents the CORDIC Algorithm, which has been implemented as an virtual component (IP core) in a VHDL simulation environment. The core is packaged as a soft (VHDL) macro and it implements all transcenden-tal functions. Analysis of the accuracy of the algorithms implemented shows that the CORDIC functions are equivalent to the accuracy of a Pentium coprocessor.
Platform: |
Size: 117760 |
Author: 赵平 |
Hits:
Description: 介绍了TMS320C64X系列DSP内部Turbo码协处理器（TCP）的结构和算法。给出了使用TCP实现符合3GPP协议的Turbo译码的程序流程，实现了一种使用中断服务程序控制的高校处理流程，最后给出了TCP译码性能与处理时延的硬件实现结果，并做出了一定的分析-TMS320C64x series DSP introduce the Turbo code internal coprocessor (TCP) structures and algorithms. Realize the use of TCP is given in line with the 3GPP agreement Turbo decoding process flow to achieve a break in service use of colleges and universities deal with flow control, and finally gives the TCP decoding performance and hardware implementation of the deal with time-delay results, and to do a certain amount of analysis
Platform: |
Size: 226304 |
Author: ynhuyong |
Hits:
Description: 介绍arm的协处理器，对于想了解arm的人很有帮助的。-Introduction arm of the co-processor, for those who would like to know the arm very helpful.
Platform: |
Size: 367616 |
Author: tang |
Hits:
Description: 现在韩国最大的协处理器厂商Mtekvison的主打产品MV8650 产品的datasheet，对使用该处理器的厂家开发驱动程序有很多帮助-Now Korea s largest manufacturers Mtekvison coprocessor s flagship product MV8650 products datasheet, on the use of the processor manufacturers to develop drivers for a lot of help
Platform: |
Size: 1447936 |
Author: jian.zhang |
Hits:
Description: ARM Architecture Reference Manual
The purpose of this manual is to describe the ARM instruction set architecture, including its high code
density Thumb® subset, and three of its standard coprocessor extensions:
• The standard System Control coprocessor (coprocessor 15), which is used to control memory system
components such as caches, write buffers, Memory Management Units, and Protection Units.
• The Vector Floating-point (VFP) architecture, which uses coprocessors 10 and 11 to supply a
high-performance floating-point instruction set.
• The debug architecture interface (coprocessor 14), formally added to the architecture in ARM v6 to
provide software access to debug features in ARM cores, (for example, breakpoint and watchpoint
control).-ARM Architecture Reference Manual
The purpose of this manual is to describe the ARM instruction set architecture, including its high code
density Thumb® subset, and three of its standard coprocessor extensions:
• The standard System Control coprocessor (coprocessor 15), which is used to control memory system
components such as caches, write buffers, Memory Management Units, and Protection Units.
• The Vector Floating-point (VFP) architecture, which uses coprocessors 10 and 11 to supply a
high-performance floating-point instruction set.
• The debug architecture interface (coprocessor 14), formally added to the architecture in ARM v6 to
provide software access to debug features in ARM cores, (for example, breakpoint and watchpoint
control).
Platform: |
Size: 3492864 |
Author: wazzup |
Hits:
Description: The uM-FPU V3.1 chip is a 32-bit floating point coprocessor that can be easily interfaced with PIC microcontrollers,
Platform: |
Size: 327680 |
Author: |
Hits:
Description: We present elliptic curve cryptography (ECC) coprocessor,
which is dual-field processor with projective
coordinator. We have implemented architecture for scalar
multiplication, which is key operation in elliptic curve
cryptography. Our coprocessor can be adapted both prime field
and binary field, also contains a control unit with 256 bit serial
and parallel operations , which provide integrated highthroughput
with low power consumptions. Our scalar multiplier
architecture operation is perform base on clock rate and produce
better performance in term of time and area compared to similar
works. We used Verilog for programming and synthesized using
Xilinx Vertex II Pro devices. Simulation was done with Modelsim
XE 6.1e, VLSI simulation software from Mentor Graphics
Corporation especially for Xilinx devices.
Platform: |
Size: 116736 |
Author: 陳曉慧 |
Hits:
Description: 自己编写的单周期16位乘法器源代码，作为普通51单片机的“协处理器”可以实现普通51的实时音频FFT-16bit multiplier source code I have written a single cycle, as the ordinary 51 single-chip coprocessor can achieve a common 51 real-time audio FFT
Platform: |
Size: 827392 |
Author: changjing |
Hits:
Description: ARM Architecture Reference Manual
The purpose of this manual is to describe the ARM instruction set architecture, including its high code
density Thumb® subset, and three of its standard coprocessor extensions:
• The standard System Control coprocessor (coprocessor 15), which is used to control memory system
components such as caches, write buffers, Memory Management Units, and Protection Units.
• The Vector Floating-point (VFP) architecture, which uses coprocessors 10 and 11 to supply a
high-performance floating-point instruction set.
• The debug architecture interface (coprocessor 14), formally added to the architecture in ARM v6 to
provide software access to debug features in ARM cores, (for example, breakpoint and watchpoint
control).-ARM Architecture Reference Manual
The purpose of this manual is to describe the ARM instruction set architecture, including its high code
density Thumb® subset, and three of its standard coprocessor extensions:
• The standard System Control coprocessor (coprocessor 15), which is used to control memory system
components such as caches, write buffers, Memory Management Units, and Protection Units.
• The Vector Floating-point (VFP) architecture, which uses coprocessors 10 and 11 to supply a
high-performance floating-point instruction set.
• The debug architecture interface (coprocessor 14), formally added to the architecture in ARM v6 to
provide software access to debug features in ARM cores, (for example, breakpoint and watchpoint
control).
Platform: |
Size: 3421184 |
Author: Pavel |
Hits:
Description: LKT4101 防抄板专用协处理器芯片采用专用的智能卡芯片平台，内置凌科芯安公司自主开发的嵌入式系统，专门为保护用户代码，防止非法访问和外部攻击而设计的新一代安全芯片。处理器使用8051内核，采用串口通讯协议，用户可以把主要算法放到芯片内部，编程语言基于标准C，开发简单方便，同时，内部大容量的数据空间可作为用户扩展数据存储器，存放重要特征数据。-LKT4101 anti-copy board dedicated coprocessor chip dedicated smart card chip platform, a new generation of security chip built-in van den Brink core security company independently developed embedded systems, specifically designed to protect the user code, to prevent unauthorized access and external attacks. 8051 core processor, using the serial communication protocol, user main algorithm onto the chip' s internal programming language based on standard C, the development of simple and convenient at the same time, large capacity internal data space can be used as a user extended data memory, to store important feature data .
Platform: |
Size: 14336 |
Author: 曹铁 |
Hits:
Description: cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator MIPS floating point support
Platform: |
Size: 7168 |
Author: yosingkon |
Hits:
Description: 一种通用可重构处理器的设计，协处理器，本文详细介绍了可重构系统的知识-A universal reconfigurable processor design, the coprocessor, This paper describes the knowledge reconfigurable systems
Platform: |
Size: 1051648 |
Author: kaus |
Hits:
Description: MAPPER86/87.A DX MAP DRAWING and Propagation Program for IBM PC Compatibles with graphics capability (Numerical Coprocessor version, Basic source code included)
Platform: |
Size: 38912 |
Author: proper |
Hits:
Description: a MIPS coprocessor 1 (fpu) instruction emulator for Linux.
Platform: |
Size: 10240 |
Author: minhingsai |
Hits:
Description: a MIPS coprocessor 1 (FPU) instruction emulator.
Platform: |
Size: 10240 |
Author: sonykcs |
Hits:
Description: TI公司AM437x Sitara™ Processors
TI AM437x高性能处理器基于ARM cortex - a9核心。
与3 d图形加速处理器增强丰富的图形用户界面,以及一个为确定的协处理器,实时处理包括工业通信协议,如
现场总线,EtherCAT EnDat等等。设备支持高级操作系统(HLOS)。从钛Linux® 是免费的。其他HLOSs可从网络和电信的设计生态系统合作伙伴。-The TI AM437x high-performance processors are based on the ARM Cortex-A9 core.
The processors are enhanced with 3D graphics acceleration for rich graphical user interfaces, as well as a
coprocessor for deterministic, real-time processing including industrial communication protocols, such as
EtherCAT, PROFIBUS, EnDat, and others. The devices support high-level operating systems (HLOS).
Linux® is available free of charge TI. Other HLOSs are available TI s Design Network and
ecosystem partners.
Platform: |
Size: 1602560 |
Author: 郭超 |
Hits:
Description: we focus on the usage of the Intel Xeon Phi platform as a coprocessor in the offload programming model. We talk about the explicit offload model based on compiler pragmas, explaining how to offload functions, local scalars and arrays of known size, and how to do data marshalling for pointer-based arrays in C and C++. Additional topics include fall-back to host, using multiple coprocessors, retaining memory buffers and data on coprocessors between offloads, overlapping communication and computation with asynchronous offload, and using environment variables for offload control. The Intel proprietary API called LEO (Language Extensions for Offload) is compared with the standard-based API for offload in OpenMP 4.0. Shared virtual memory model for offload is briefly introduced.-我们关注的英特尔Xeon Phi平台的使用作为协处理器卸载编程模型。我们谈论的显式卸载模型基于编译器编译，解释如何卸载功能，当地的标量和已知大小的数组，和如何做数据编组在基于C和C++数组的指针。其他主题包括回到主机，使用多个处理器，保留内存缓冲区和数据处理器之间的重叠与卸载卸载，异步通信和计算，并将控制使用环境变量。英特尔专有的API调用的狮子座（用于卸载语言扩展）与基于API标准OpenMP 4卸载。虚拟共享存储模型，将简要介绍。
Platform: |
Size: 41984 |
Author: 黄雪 |
Hits:
Description: GSM Channel Equalization
This application note describes the theory and implementation of GSM channel equalization and channel decoding algorithms using the Freescale MSC8126 Viterbi coprocessor (VCOP). It also examines the theory behind the soft output Viterbi algorithm (SOVA) assisted by the VCOP. Code examples illustrate how the VCOP performs channel equalization and the SOVA algorithm. A set of suggested design practices for VCOP usage is followed by a discussion of the VCOP driver, which provides a simple, easy interface to the VCOP. Examples of driver usage cover GSM equalization, channel decoding, and SOVA. The source code and the header file for the VCOP driver are also presented.
Platform: |
Size: 402432 |
Author: JRB |
Hits: