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[VHDL-FPGA-Verilogdds_using_FPGA

Description: 利用FPGA实现DDS经过编译没有错误。编译环境为QuartusII7.2,该环境集成了IP核,可以提高开发效率。-FPGA realization of the use of DDS compiled no errors. Compiler environment QuartusII7.2, the environment integrated IP core, can improve the development efficiency.
Platform: | Size: 100352 | Author: 白涛 | Hits:

[VHDL-FPGA-Verilogmatlab_for_FPGA_mif_coe

Description: 利用matlab生成sin、cos、sinc和insert等mif文件-Using matlab to generate a variety of mif file
Platform: | Size: 103424 | Author: leixiaoqiang | Hits:

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