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[Other resource] COUNT10

Description: 一个十进制计数器的vhdl程序，大家可以参考，已经经过编译了
Platform: | Size: 108946 | Author: wangyan | Hits:

[VHDL-FPGA-Verilog] COUNT10

Description: 一个十进制计数器的vhdl程序，大家可以参考，已经经过编译了-A decimal counter VHDL process, everyone can refer to, has been compiled
Platform: | Size: 108544 | Author: wangyan | Hits:

Description: 设计一个十进制计数器，具有显示位置随计数时钟在八个数码管中左右滚动的功能。-The design of a decimal counter, with a display position count with the clock in eight digital tube rolling around function.
Platform: | Size: 1024 | Author: 庄子不逍遥 | Hits:

[VHDL-FPGA-Verilog] count10

Description: 用vhdl编写的十进制计数器，内部说明详细。-Prepared using VHDL decimal counter, the internal description in detail.
Platform: | Size: 152576 | Author: 雪花 | Hits:

[VHDL-FPGA-Verilog] count10

Description: 基于Quartus II的十进制加法计数器的项目设计，包含了项目文件和VHDL源代码-Quartus II based on the decimal adder counter the project design, including project documents and VHDL source code
Platform: | Size: 1406976 | Author: xiexuan | Hits:

[VHDL-FPGA-Verilog] count10

Description: 基于vhdl语言的10进制的计数器程序，应该有用-Vhdl-based language program for 10 binary counter
Platform: | Size: 325632 | Author: 郭文记 | Hits:

[FlashMX] count10

Description: 十进制计数器自己尝试编辑的，可以-jk flip-flop, try to edit their own, using state machine to achieve, you can-Decimal counter his attempt to edit, and can-jk flip-flop, try to edit their own, using state machine to achieve, you can
Platform: | Size: 106496 | Author: liu jian ming | Hits:

[VHDL-FPGA-Verilog] count10

Description: 在quartus环境下，开发的一个10位的计数器，性能可靠，可用作初学者的学习-Quartus environment in the development of a 10-bit counter, reliable performance, can be used for beginners to learn
Platform: | Size: 251904 | Author: jim | Hits:

[VHDL-FPGA-Verilog] count10

Description: 10进制计数器,用于一般的计数、计时等基本元件。-ten counter
Platform: | Size: 35840 | Author: huang | Hits:

[VHDL-FPGA-Verilog] COUNT10

Description: 基于FPGA的一个带有异步复位和同步时钟使能的十进制加法计数器的设计，QuartusII编译通过，采用VHDL语言编写。-Based on FPGA with a reduction of asynchronous and synchronous clock can make the decimal additions counter design, QuartusII compile, USES the VHDL language.
Platform: | Size: 242688 | Author: 左云华 | Hits:

[Other] count10

Description: 利用VHDL编写的十进制计数器，测试成功，可以使用-Use VHDL to write decimal counter, the test is successful, you can use
Platform: | Size: 452608 | Author: wangsong | Hits:

[VHDL-FPGA-Verilog] Chapter4

Description: Chapter4文件夹：（1）实验1：编码器实验，完整的设计工程文件在CODER文件夹下（2）实验2：译码器实验，完整的设计工程文件在DECODER7文件夹下（3）实验3：加法器实验，完整的设计工程文件在ADDER和ALU文件夹下（4）实验4：乘法器实验，完整的设计工程文件在4BITMULT文件夹下（5）实验5：寄存器实验，完整的设计工程文件在SHIFT8R和SHIFT8文件夹下（6）实验6：计数器实验，完整的设计工程文件在COUNT10文件夹下（7）实验7：分频器实验，完整的设计工程文件在ODD_DEV_F文件夹下（8）实验8：存储器实验，完整的设计工程文件在RAM文件夹下-Chapter4 folder: (1) Experiment 1: encoder experiment, the complete design engineering documents in the the CODER folder (2) Experiment 2: decoder experiments, complete design engineering documents under the folder DECODER7 (3) Experiment 3 : adder experiment, complete design engineering documents in the the ADDER and ALU folder (4) Experiment 4: Multiplier experiment, a complete design engineering documents in 4BITMULT folder (5) Experiment 5: register experiment complete design engineering file under the SHIFT8R and SHIFT8 folder (6) Experiment 6: counter experiment, a complete design the project file the COUNT10 folder (7) Experiment 7: divider experimental design the project file the ODD_DEV_F folder (8 ) Experiment 8: memory experiments, complete design project files in the the RAM file folder under
Platform: | Size: 1654784 | Author: boyzone | Hits:

[Web Server] count10

Description: 具有占系统资源少、易二次编写、多用户、在线申请、即时开通、多样式、多功能等优点，并提供全面的统计报表-It has accounted for less system resources, easy to write the second, multi-user, online application, immediate opening, multi-style, multi-function, etc., and provide comprehensive statistical reports
Platform: | Size: 84992 | Author: mcujc422 | Hits:

[VHDL-FPGA-Verilog] counter10

Description: vhdl编写的十进制计数器，名字叫count10，已配好引脚(VHDL's decimal counter, named count10, has been matched with a pin)
Platform: | Size: 1422336 | Author: li 234 | Hits:

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[Other resource] COUNT10

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[VHDL-FPGA-Verilog] Chapter4

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