Search - counter vh

Search - counter vh - List

[Other resource] sdgshjd DL : 0: 数字系统设计这是有关的相关源代码，有简易CPU 除法器、计数器等 ...[fpdiv_vhdl.rar] - 四位除法器的vhdl源程序 [vhdl范例.rar] - 最高优先级编码器8位相等比较器三人表决器（三种不同的描述方式）加法器描述 8位总线收发器：74245 （注2）地址译码（for m68008）多路选择器（使 BR> ... -Digital System Design This is the underlying source code, a simple CPU divider. Counter etc. ... [fpdiv_vhdl.rar] - 4 division of vhdl source [vh dl example. rar] - highest priority encoder compared to eight for phase three of the vote (the three different description ) Adder Description eight bus transceiver : 74245 (Note 2) address decoder (for m68008) Multiple choice (so that BR
Update : 2008-10-13 Size : 838byte Publisher : 张瑞
[VHDL-FPGA-Verilog] N_counter_VHDL DL : 0: 任意N进制分频器的标准VHDL代码（原创）-arbitrary N divider 229 standard VHDL code (original)
Update : 2025-03-11 Size : 1kb Publisher : 汤维
[MPI] sdgshjd DL : 0: 数字系统设计这是有关的相关源代码，有简易CPU 除法器、计数器等 ...[fpdiv_vhdl.rar] - 四位除法器的vhdl源程序 [vhdl范例.rar] - 最高优先级编码器8位相等比较器三人表决器（三种不同的描述方式）加法器描述 8位总线收发器：74245 （注2）地址译码（for m68008）多路选择器（使 BR> ... -Digital System Design This is the underlying source code, a simple CPU divider. Counter etc. ... [fpdiv_vhdl.rar]- 4 division of vhdl source [vh dl example. rar]- highest priority encoder compared to eight for phase three of the vote (the three different description ) Adder Description eight bus transceiver : 74245 (Note 2) address decoder (for m68008) Multiple choice (so that BR
Update : 2025-03-11 Size : 1kb Publisher : 张瑞
[Software Engineering] 74161 DL : 0: 计数器74161功能测试电路状态机程序。该程序是功能测试电路的核心。-Counter 74161 functional test circuit state machine procedures. The program is the core of functional test circuit.
Update : 2025-03-11 Size : 1kb Publisher : 左猛
[Software Engineering] 4CounterMod8Comportamental DL : 0: Counter Module 8 using comportamental description in VHDL
Update : 2025-03-11 Size : 1.46mb Publisher : Alejandro
[VHDL-FPGA-Verilog] zz DL : 0: 键控加/减计数器,将20MHz系统时钟经分频器后可得到5M、1M、100K、10K、5K、1K、10Hz、1Hz -Keying increase/decrease counter to 20MHz system clock by the divider available after 5M, 1M, 100K, 10K, 5K, 1K, 10Hz, 1Hz
Update : 2025-03-11 Size : 478kb Publisher : zuoshu_2008
[VHDL-FPGA-Verilog] counter-CPLD DL : 0: CPLD学习，用VHDL,应用EPM7032,一个138，373和273的例程-CPLD study, using VHDL, application EPM7032, one of the routines 138,373, and 273
Update : 2025-03-11 Size : 98kb Publisher : YAN
[VHDL-FPGA-Verilog] 74LS160 DL : 0: 源码，VHDL语言编写的74LS160计数器-Source code, VHDL language of the 74LS160 counter
Update : 2025-03-11 Size : 49kb Publisher : 周
[VHDL-FPGA-Verilog] 8253 DL : 0: 8253计数器接口电路 intel8253是NMOS工艺制成的可编程计数器/定时器，有几种芯片型号，外形引脚及功能都是兼容的，只是工作的最高计数速率有所差异-8253 counter interface circuit
Update : 2025-03-11 Size : 2.32mb Publisher : keven