Search - counter vhdl

[VHDL-FPGA-Verilog] anjian

Description: 按键输入模块（key）： --可编程延时发生器（数字同步机）的前端输入模块：0－9十个数字键按键输入模块原型 --前端模块：消抖 --对i0－i9十个输入端的两点要求： --（1）输入端要保证一段时间的稳定高电平 --（2）不能同时按下两个或多于两个的键 --后级模块：1、编码；2、可变模计数器 --编码模块：8线－4线（0－8 BCD码） --可变模计数器模块：以编码模块输出的32位BCD码为模值-button input module (key) :-- programmable delay generator (digital synchronous machine) the front-end input module : 0-2-9 10 numeric keys keys input module prototype-- front-end module : Consumers quiver-- the domain-Makes 10 input of the two requirements :-- (a) input to ensure a period of stability to I-- (2) can not be pressed together two or more two keys-- after class modules : one, coding; 2, variable Die counter-- Coding modules : 8-to-four (0-8 BCD)-- Variable Mode counter modules : coding module output to the 32 BCD value to Die
Platform: | Size: 2048 | Author: 汪汪 | Hits:

[VHDL-FPGA-Verilog] bicount

Description: 完整的双向计数器VHDL 程序大家参考-integrity of the two-way counter VHDL reference procedures
Platform: | Size: 1024 | Author: 潘科良 | Hits:

[VHDL-FPGA-Verilog] VHDL.sheji.2

Description: 电子时钟VHDL程序与仿真 10进制计数器设计与仿真 6进制计数器设计与仿真-electronic clock procedures and VHDL simulation Decimal counter design and simulation of six NUMBER Design and Simulation
Platform: | Size: 59392 | Author: 少龙 | Hits:

[VHDL-FPGA-Verilog] counter1

Description: vhdl 计数器源程序，大家看看吧 vhdl 计数器源程序，大家看看吧-vhdl counter source, we see it vhdl counter source, we see it
Platform: | Size: 1024 | Author: 张三 | Hits:

[Other] ptc

Description: PWM/TIMER/COUNTER VHDL IP core
Platform: | Size: 272384 | Author: hehilon | Hits:

[VHDL-FPGA-Verilog] count16

Description: count16.vhd 16位BCD计数器VHDL源程序-count16.vhd 16 BCD counter VHDL source
Platform: | Size: 1024 | Author: 杨奎元 | Hits:

[VHDL-FPGA-Verilog] shijizhi

Description: 十进制加法计数器.VHDL程序,可在Quratus 2中运行-Decimal adder counter. VHDL program can be run Quratus 2
Platform: | Size: 166912 | Author: 晨曦 | Hits:

[Other] Some_VHDL_Examples

Description: 几个VHDL的例子，供大家参考，包括寄存器的设计，同步二进制计数器的设计，时钟计数器的设计等，个人觉得很有用处-Several examples of VHDL for reference, including the register of designs, synchronous binary counter design, the design of the clock counter, personal feel that is very useful
Platform: | Size: 168960 | Author: 钱 | Hits:

[VHDL-FPGA-Verilog] counter

Description: VHDL计数器的TestBench，适合初学者-VHDL counter TestBench, suitable for beginners
Platform: | Size: 1024 | Author: hbsun | Hits:

[VHDL-FPGA-Verilog] COUNT10

Description: 一个十进制计数器的vhdl程序，大家可以参考，已经经过编译了-A decimal counter VHDL process, everyone can refer to, has been compiled
Platform: | Size: 108544 | Author: wangyan | Hits:

[Other Embeded program] pinlvji

Description: 利用VHDL语言写的0到100MHZ频率计，只通过仿真，未在实验台验证，仅供参考-VHDL language using the 0 to 100MHz frequency counter, only through simulation, not in the test-bed validation, for reference only
Platform: | Size: 2048 | Author: zengfan155 | Hits:

[VHDL-FPGA-Verilog] binarycount

Description: 异步复位、同步置数的四位二进制计数器的VHDL源文件-Asynchronous reset, synchronous purchase the number of binary counter 4 of the VHDL source files
Platform: | Size: 1024 | Author: chenwen | Hits:

[VHDL-FPGA-Verilog] counter

Description: 计数器的VHDL设计，已经在FPGA上验证-VHDL counter design, has been tested in the FPGA
Platform: | Size: 1024 | Author: chen | Hits:

[Software Engineering] VHDL

Description: 在电子技术中，频率是最基本的参数之一，又与许多电参量的测量方案、测量结果都有十分密切的关系，因此频率的测量就显得更为重要。测量频率的方法有多种,其中电子计数器测量频率具有精度高、使用方便、测量迅速，以及便于实现测量过程自动化等优点，是频率测量的重要手段之一。在本次毕业设计中我们选择使用单片机来制作数字频率计，并在实际制作中采用了直接测频法。利用延时产生的时基门控信号来控制闸门，通过在单位时间内计数器记录下的脉冲个数计算出输入信号的频率，最终送入LCD中显示。这样制作出来的频率计不仅可以满足设计题目的参数要求，而且具有了单片机的稳定性和成熟性，且控制能力强，是一种低成本，高可靠的设计方案。-In electronic technology, the frequency is one of the most basic parameters, but also with a number of electrical parameters of the measurement program, the measurement results have a very close relationship between the frequency of measurement, therefore it is even more important. Measurement of the frequency of a number of means, electronic measurement of the frequency counter with high precision, easy to use, rapid measurement, and measurement is easy to realize the advantages of process automation is an important means of measuring the frequency of one. Graduates in this design we have chosen to make use of single-chip digital frequency meter, and used in the actual production of a direct frequency measurement method. Delay arising from the use of gated time-base signal to control the gate time in units of the pulse counter to record the number of calculated frequency of the input signal, and ultimately into the LCD display. This produced not only the frequency of the parameters to
Platform: | Size: 220160 | Author: 张林锋 | Hits:

[VHDL-FPGA-Verilog] counter

Description: 基于VHDL的计数代码，可用于FPGA芯片对步进电机的控制-Count based on VHDL code for FPGA chips can be used to control stepper motor
Platform: | Size: 1024 | Author: sun | Hits:

[VHDL-FPGA-Verilog] counter

Description: -- Mod-16 Counter using JK Flip-flops -- Structural description of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal named tied_high into a package named jkpack . -- The counter design uses the package jkpack , giving it access to the components and the signal declared within the package. -- The flip-flops and AND-gates are wired together to form a counter. -- Notice the use of the keyword OPEN to indicate an open-cct output port. -- some syntax can t be synthesized,it s for simulation only,such as "AFTER 5 ns"--- Mod-16 Counter using JK Flip-flops -- Structural description of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal named tied_high into a package named jkpack . -- The counter design uses the package jkpack , giving it access to the components and the signal declared within the package. -- The flip-flops and AND-gates are wired together to form a counter. -- Notice the use of the keyword OPEN to indicate an open-cct output port. -- some syntax can t be synthesized,it s for simulation only,such as "AFTER 5 ns"
Platform: | Size: 1024 | Author: jgc | Hits:

[VHDL-FPGA-Verilog] VHDL-3BCD

Description: 3位BCD码的计数显示电路。BCD码计数电路从0计到9然后返回到0从新计数。3位BCD码计数器可以实现从0到999的十进制计数。要将计数过程用七段显示LED数码管显示出来，这里采用动态分时总线切换电路对数码管进行扫描，对数码管依次分时选中进行输出计数的个、十、百位的数据。-3 BCD code count display circuit. BCD code counting circuit count from 0 to 9 and then back to 0 from the new count. 3 BCD code counter can be achieved from 0 to 999 decimal count. Counting process with seven segment displays to LED digital tube displays, where dynamic time-sharing digital bus switch circuit to scan, followed by time-sharing of digital output selected for a count of ten, hundred bits of data.
Platform: | Size: 56320 | Author: will li | Hits:

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[VHDL-FPGA-Verilog] anjian

[VHDL-FPGA-Verilog] bicount

[VHDL-FPGA-Verilog] VHDL.sheji.2

[VHDL-FPGA-Verilog] counter1

[Other] ptc

[VHDL-FPGA-Verilog] count16

[VHDL-FPGA-Verilog] shijizhi

[Other] Some_VHDL_Examples

[VHDL-FPGA-Verilog] counter

[VHDL-FPGA-Verilog] COUNT10

[Other Embeded program] pinlvji

[VHDL-FPGA-Verilog] binarycount

[VHDL-FPGA-Verilog] counter

[Software Engineering] VHDL

[VHDL-FPGA-Verilog] counter

[VHDL-FPGA-Verilog] counter

[VHDL-FPGA-Verilog] VHDL-3BCD

[VHDL-FPGA-Verilog] Mode-variable-counter-vhdl

[VHDL-FPGA-Verilog] Adder and Counter VHDL

[VHDL-FPGA-Verilog] counter

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