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Description: 用DA转换＋比较器的方法对外界模拟信号进行检测，同时这种联合装置加上CPLD可以代替低频AD转换器的功能-+ DA converters used for the comparison to the outside world analogue signal detection, at the same time with the Joint CPLD device can replace low-frequency AD converter functions
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Size: 2048 |
Author: 赵天 |
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Description: 此射频合成信号源的设计，基于DDS芯片AD9954 和CPLD，此设计论文对设计方案有详细介绍-Synthesis of this RF signal source design, based on the DDS chip AD9954 and CPLD, Design of this thesis is the design plan detailed
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Size: 970752 |
Author: 王勇军 |
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Description: TI公司的AD8361的VHDL控制程序，可实现CPLD的采集。-TI s AD8361 the VHDL control procedures, the acquisition can be realized CPLD.
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Size: 1024 |
Author: 祝箭 |
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Description: 非常好的原代码，利用cpld控制0809采样，利用maxplus平台开发-Very good original code, the use of CPLD Control 0809 sampling, the use of platform development maxplus
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Size: 2101248 |
Author: xiaoxu |
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Description: 2812开发板原理图和使用说明，板上有AD,MIC,CPLD，以太网，按键，usb-2812 development board schematics and use of that board have AD, MIC, CPLD, Ethernet, keys, usb
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Size: 3030016 |
Author: 林仲逸 |
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Description: CPLD EPM7256原理图PCB图，已经校验，没有什么问题，制版既可。-CPLD EPM7256 Schematic diagram PCB have been checking, there was no problem with either plate.
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Size: 49152 |
Author: 马爽 |
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Description: 通过使用CPLD来控制AD转换,实现实时采集数据 -Through the use of CPLD to control the AD conversion, real-time data collection
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Size: 1024 |
Author: 张坤 |
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Description: TMS320F28335开发例程,包括USB,串口,AD,DA-TMS320F28335 development of routines, including USB, serial, AD, DA
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Size: 5382144 |
Author: |
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Description: Serial ADC Interface write in VHDL based on xilinx cpld
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Size: 33792 |
Author: jiang |
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Description: ad取样，经由cpld处理，存入ram 1000点并由串行的da进行还原-ad sampling, by the CPLD deal, deposited by the serial ram 1000 points to restore the da
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Size: 180224 |
Author: |
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Description: 这是利用VHDL语言编写的关于ADC0809的程序，编的很不错-This is the use of VHDL language on the ADC0809 procedure, made a very good
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Size: 1024 |
Author: 王盗大 |
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Description: 用VHDL语言写的程序包含如下功能：1.键盘扫描2.控制AD转换3.产生PWM信号与51系列CPU接口，接在51地址数据总线上，单片机通过访问地址总线上的数据寄存器来控制CPLD-VHDL language used to write the procedure that contains the following functions: 1. Keyboard scan 2. Control of AD converters 3. Generate PWM signals with the 51 series CPU interface, and then in the address data bus 51, the single-chip by visiting the address bus data Register to control the CPLD
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Size: 455680 |
Author: liubaogui |
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Description: 用cpld控制时序通过usb传送数据到pc机的vhdl源码，用于一款心电图机。
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Size: 203776 |
Author: 聂永波 |
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Description: 使用FPGA/CPLD设置语音AD、DA转换芯片AIC23，FPGA/CPLD系统时钟为24.576MHz
1、AIC系统时钟为12.288MHz，SPI时钟为6.144MHz
2、AIC处于主控模式
3、input bit length 16bit output bit length 16bit MSB first
4、帧同步在96KHz-The use of FPGA/CPLD set voice AD, DA conversion chip AIC23, FPGA/CPLD system clock for the 24.576MHz 1, AIC system clock is 12.288MHz, SPI clock is 6.144MHz 2, AIC is in master mode 3, input bit length 16bit output bit length 16bit MSB first 4, frame synchronization at 96KHz
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Size: 2048 |
Author: 张键 |
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Description: 从零开始学CPLD和VerilogHDL编程技术，包括实验板原理图和实验源代码。-VerilogHDL learn from scratch and CPLD programming technologies, including board schematics and test source code.
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Size: 3163136 |
Author: 宋大力 |
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Description: SPI 的FPGA控制源代码，用于一般通用的SPI技术，FPGA/CPLD控制的AD数据采集-SPI control course code
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Size: 1024 |
Author: luxiaogang |
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Description: 51单片机+CPLD结构，小板上集成了发光二极管，蜂鸣器，数码管，红外接收头，继电器，实时时钟，按键，AD（TLC1549），DA（TLC5615），232串口，LCD1602接口，LCD12864接口，单片机和CPLD引脚扩展接口，集成5V稳压电源，USB电源接口等功能。 -hhhhhhhhhhhhhhhhhhhhhhhhhhhhh
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Size: 194560 |
Author: 胡俊 |
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Description: ad采集的小模块，实现串口转并口的功能，串口是SPI的接口-ad collector modoudle ad ad ad ad ad da da da da shuzi moni moni shuzi caiji caiji caiji caiji caiji caiji caiji
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Size: 32768 |
Author: ninglige |
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Description: 2407A 内置 16 通道10 位AD 转换器，在 00IC2407＋CPLD 实验板上只扩展两通道，分
别是第0 通道和第8通道，DSP 能承受的A/D 输入信号是0－3.3V，在00IC2407+CPLD 实
验板上没有单独采用基准源，直接使用系统的3.3V作为A/D 转换器的基准信号。 -Built-2407A 16-channel 10-bit AD converter, in 00IC2407+ CPLD experiment board extended only two channels, namely, 0-channel and 8-channel, DSP can withstand the A/D input signal is 0-3.3V, in 00IC2407+ CPLD There is no separate test board with reference to directly use the system' s 3.3V, as A/D converter reference signal.
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Size: 79872 |
Author: lizhenli |
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Description: CPLD + CAN总线改造，采用CPLD 进行编程，实现移相编码和电机功率输出， CAN总线进行数据通讯，使各节点独立工作又集中管理，实现集散控制。节点电机调速方案中，微控制器选用8位高性能微转换器ADμC812，逻辑与伺服控制采用全数字化方式，晶闸管主电路触发器选用ALTERA公司的 EPM7256S CPLD来完成。-CPLD+ CAN bus transformation, using CPLD for programming, coding and phase motor power output, CAN bus for data communication, so that each node independently and focus on management, distributed control. Node in the motor control program, use 8-bit high performance microcontroller micro-converter ADμC812, logic and all-digital servo control mode, the main thyristor trigger circuit used ALTERA company EPM7256S CPLD to complete.
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Size: 67584 |
Author: 李飞 |
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