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Description: ide的低层驱动程序。一个工程(cpld+dsp)的一部分。-ide the lower driver. A project (cpld + dsp) part.
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Size: 58655 |
Author: 傅文祥 |
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Description: cpld+dsp
有需要的可以看看
cpld+dsp
有需要的可以看看 cpld+dsp
有需要的可以
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Size: 191900 |
Author: samuel |
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Description: JTAG仿真器CPLD -JTAG Emulator CPLD
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Size: 345088 |
Author: 李秉 |
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Description: 该工程文件实现ARM系统中CPLD的逻辑工作,起到外围资源的逻辑地址译码功能-realization of the project document ARM system CPLD logic, external resources have address decoding logic function
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Size: 117760 |
Author: 王希 |
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Description: 用maxplus2实现的一种通用逻辑模块,背景是一个基于dsp的嵌入式开发板,上面的逻辑模块全用cpld实现。此模块可以供以后的嵌入式开发作参考。-maxplus2 achieved using a common logic modules, background is a DSP-based embedded development board, the above logic modules throughout cpld achieve. This module can be embedded for the future development for reference.
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Size: 435200 |
Author: hanchong |
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Description: dsp下载器cpld程序
感兴趣的朋友可以下来-dsp downloader cpld procedures interested friends can see down
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Size: 140288 |
Author: Scofield |
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Description: dsp与cpld的连接原理图,华绑的哦!-dsp and cpld connection diagram, China tied Oh!
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Size: 15360 |
Author: 冬虫草 |
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Description: fpga/CPLD开发管理Digit-Serial DSP Functions-fpga/CPLD Development and Management of Digit-Serial DSP Functions
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Size: 2659328 |
Author: liuandy |
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Description: ARM,DSP,FPGA的区别:详细介绍了ARM,DSP,FPGA/CPLD的异同。-ARM, DSP, FPGA distinction: a detailed introduction of the ARM, DSP, FPGA/CPLD the similarities and differences.
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Size: 88064 |
Author: 韩彬 |
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Description: TMS320VC5502 DSP BootLoad源码 包括CPLD源码-TMS320VC5502 DSP BootLoad including CPLD source source
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Size: 455680 |
Author: zsw |
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Description: DSP与CPLD通信方法 有需要的请下载-DSP and CPLD communication methods are needed, please download
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Size: 59392 |
Author: 李超 |
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Description: MAX II CPLD具有灵活的可编程接口,合并了分立的FLASH存储器件,能快速和容易地配置FPGA,DSP,ASIC等。本中文手册将让用户对CPLD有一个宏观的认识。-MAX II CPLD with a flexible programmable interface, the merger of the separation of FLASH memory, can quickly and easily configure the FPGA, DSP, ASIC, etc.. Chinese manual will allow users to have a macro on the CPLD awareness.
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Size: 990208 |
Author: pantree |
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Description: 用DSP进行语音压缩的一个开发实例(PCI总线)。详细介绍了PCI总线以及语音压缩数字信号处理系统的软、硬件系统设计方案及架构-DSP for voice compression using the example of a development (PCI bus). Detailed information on PCI bus, as well as voice compression digital signal processing system software and hardware system design and architecture
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Size: 332800 |
Author: PB |
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Description: TI 原装开发板 DM6467 原理图 CPLD 给需要的人-TI original DM6467 development board CPLD schematic to those who need
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Size: 446464 |
Author: csallon |
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Description: 学习fpga/cpld的书籍,介绍quartus 2及dsp builder的使用,-Learning fpga/cpld books, introduced quartus 2 and dsp builder use,
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Size: 14001152 |
Author: 彭武军 |
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Description: dsp 2812 开发板,包含SCH和PCB-dsp 2812 developing board,including SCH and PCB
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Size: 24576 |
Author: liu |
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Description: 零零电子2407+cpld开发板的源程序,可用于参考学习-Page E-2407+ cpld development board of the source, can be used to refer to learning
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Size: 967680 |
Author: zhaowenjun |
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Description: 00IC2407+CPLD板上选用的DA转换器是TI公司的TLC5620,TLC5620是串行4通道8位
DA 转换器,DSP 通过 SPI 与其接口,TLC5620 的工作频率是 1MHZ,所有 DSP 的 SPI也必须设置位1MHZ, -00IC2407+ CPLD DA converter board is selected TI' s TLC5620, TLC5620 is a serial 4-channel 8-bit DA converters, DSP and its interface, through the SPI, TLC5620 operating frequency is 1MHZ, all the DSP' s SPI must also be set bit 1MHZ,
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Size: 67584 |
Author: lizhenli |
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Description: 2407A 内置 16 通道10 位AD 转换器,在 00IC2407+CPLD 实验板上只扩展两通道,分
别是第0 通道和第8通道,DSP 能承受的A/D 输入信号是0-3.3V,在00IC2407+CPLD 实
验板上没有单独采用基准源,直接使用系统的3.3V作为A/D 转换器的基准信号。 -Built-2407A 16-channel 10-bit AD converter, in 00IC2407+ CPLD experiment board extended only two channels, namely, 0-channel and 8-channel, DSP can withstand the A/D input signal is 0-3.3V, in 00IC2407+ CPLD There is no separate test board with reference to directly use the system' s 3.3V, as A/D converter reference signal.
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Size: 79872 |
Author: lizhenli |
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Description: dsp控制lcd的例子 共享给大家 希望有用到的地方-examples of dsp control lcd
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Size: 158720 |
Author: richie li |
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