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Description: 本教程定位于FPGA/CPLD的快速入门。以ALTERA公司的芯片和相应的开发软件为目标载体进行阐述，本教程阐述了ALTERA主要系列芯片PLD芯片的结构和特点以及相应的开发软件MAX和Plusa和Quartus的使用-position in the handbook FPGA / CPLD Quick Start. With Altera's chips and the corresponding development of software for the target vector elaborate, the tutorials explain the main chips Altera PLD chips on the structure and characteristics of the corresponding software development MA Plusa and X and the use Quartus
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Size: 4329224 |
Author: 小易 |
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Description: Writing Efficient C for ARM
基于ARM内核微处理器操作系统的移植
基于ARM的嵌入式开发(PDF ARM中国)
ARM+DSP+CPLD开发板
s3c2410(arm9)protel99格式的原理图和PCB图
-Writing Efficient C for ARM microprocessor-based ARM core operations transplantation of ARM-based embedded development (PDF ARM China) ARM DSP development board CPLD s 3c2410 (arm9) Protel format schematics and PCB plans
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Size: 957843 |
Author: 胡飞逸 |
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Description: Writing Efficient C for ARM
基于ARM内核微处理器操作系统的移植
基于ARM的嵌入式开发(PDF ARM中国)
ARM+DSP+CPLD开发板
s3c2410(arm9)protel99格式的原理图和PCB图-Writing Efficient C for ARM microprocessor-based ARM core operations transplantation of ARM-based embedded development (PDF ARM China) ARM DSP development board CPLD s 3c2410 (arm9) Protel format schematics and PCB plans
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Size: 507996 |
Author: 胡飞逸 |
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Description: 本教程定位于FPGA/CPLD的快速入门。以ALTERA公司的芯片和相应的开发软件为目标载体进行阐述，本教程阐述了ALTERA主要系列芯片PLD芯片的结构和特点以及相应的开发软件MAX和Plusa和Quartus的使用-position in the handbook FPGA/CPLD Quick Start. With Altera's chips and the corresponding development of software for the target vector elaborate, the tutorials explain the main chips Altera PLD chips on the structure and characteristics of the corresponding software development MA Plusa and X and the use Quartus
Platform: |
Size: 4328448 |
Author: 小易 |
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Description: Writing Efficient C for ARM
基于ARM内核微处理器操作系统的移植
基于ARM的嵌入式开发(PDF ARM中国)
ARM+DSP+CPLD开发板
s3c2410(arm9)protel99格式的原理图和PCB图
-Writing Efficient C for ARM microprocessor-based ARM core operations transplantation of ARM-based embedded development (PDF ARM China) ARM DSP development board CPLD s 3c2410 (arm9) Protel format schematics and PCB plans
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Size: 957440 |
Author: 胡飞逸 |
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Description: Writing Efficient C for ARM
基于ARM内核微处理器操作系统的移植
基于ARM的嵌入式开发(PDF ARM中国)
ARM+DSP+CPLD开发板
s3c2410(arm9)protel99格式的原理图和PCB图-Writing Efficient C for ARM microprocessor-based ARM core operations transplantation of ARM-based embedded development (PDF ARM China) ARM DSP development board CPLD s 3c2410 (arm9) Protel format schematics and PCB plans
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Size: 507904 |
Author: 胡飞逸 |
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Description: 采用MaxPlusII写的一个小时钟程序，也是供初学参考。呵呵。注///版主，开发环境里面没有MaxPlusII.-MaxPlusII used to write a small clock procedures, as well as reference for beginners. Ha ha. Note///moderator, development environment there's no MaxPlusII.
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Size: 812032 |
Author: Backy |
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Description: 介绍了如何基于CPLD开发单片机，其中详细介绍了单片机的结构和工作原理以及CPLD的详细开发技术-described how microcontroller-based CPLD development, for detailed information on the computer's structure and working principle and the detailed CPLD Development
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Size: 1156096 |
Author: 魏巍 |
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Description: MARS-7128-S CPLD开发板VHDL 源码
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Size: 2562048 |
Author: 史蒙克 |
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Description: 键盘去抖动CPLD设计经过验证,可以直接用数码管显示,同时也希望大家给于新想法-CPLD design of the keyboard to jitter verified, you can directly use digital tube display, but also hope that the new ideas to the U.S.
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Size: 123904 |
Author: tssk |
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Description: TI公司的AD8361的VHDL控制程序，可实现CPLD的采集。-TI s AD8361 the VHDL control procedures, the acquisition can be realized CPLD.
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Size: 1024 |
Author: 祝箭 |
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Description: 本文详细分析了COOLRUNNER系列CPLD的结构,特点及功能,使用VHDL语言实现数字逻辑,实现了水下冲击波记录仪电路的数字电路部分.-In this paper, a detailed analysis of the CoolRunner CPLD series structure, characteristics and functions, the use of VHDL language digital logic, the realization of the underwater shock wave logger s digital circuit part of the circuit.
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Size: 323584 |
Author: |
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Description: CAN总线资料，
CAN.sch 是protel99se格式文件
CPLD目录是7032的CPLD工程，使用MAX+PULS10.0
test目录是程序工程目录，使用ADS1.2编译该工程，load到SDRAM调试-err
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Size: 220160 |
Author: pangbai |
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Description: 对于LPC系列的ARM仿真器的制作详细说明，其中有CPLD的加密程序，protel99se的sch，PCB电路图，以及AVR的hex文件。制作出的效果和买的一样。-For the LPC series of ARM simulator produced a detailed description, including CPLD encryption procedures, protel99se of sch, PCB circuit diagrams, as well as the AVR s hex file. To produce results and to buy the same.
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Size: 115712 |
Author: ssj |
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Description: 最近收集的一些CPLD的文章，都是各大期刊上的，虽然不会有详细的设计步骤，但当些参考还是可以的，在别的地方下载也是需要花钱的，现在打包下载，给大家提供点方便。-CPLD has recently collected some of the article, are the major journals, although there will be no detailed design steps, but can still make reference to, and in other places also need to spend money to download now download package to the U.S. provide convenient points.
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Size: 3456000 |
Author: aaaa |
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Description: TI 原装开发板 DM6467 原理图 CPLD 给需要的人-TI original DM6467 development board CPLD schematic to those who need
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Size: 446464 |
Author: csallon |
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Description: 设计并调试好一个能产生”梁祝”曲子的音乐发生器，并用EDA实验开发系统（拟采用的实验芯片的型号可选Altera的MAX7000系列的 EPM7128 CPLD ，FLEX10K系列的EPF10K10LC84-3 FPGA， ACEX1K系列的 EP1K30 FPGA，Xinlinx 的XC9500系列的XC95108 CPLD，Lattice的ispLSI1000系列的1032E CPLD）进行硬件验证。
设计思路
根据系统提供的时钟源引入一个12MHZ时钟的基准频率，对其进行各种分频系数的分频，产生符合某一音乐的频率，然后再引入4HZ的时钟为音乐的节拍控制，最后通过扬声器放出来。
-Design and debug a good one can produce The Butterfly Lovers piece of music generator, and the development of EDA experimental system (to be used in models of experimental chip with optional Altera s MAX7000 series EPM7128 CPLD, FLEX10K series EPF10K10LC84-3 FPGA, ACEX1K Series The EP1K30 FPGA, Xinlinx the XC9500 series XC95108 CPLD, Lattice s ispLSI1000 series 1032E CPLD) for hardware verification. Design according to the system clock source provided by the introduction of a benchmark 12Mhz clock frequency and its various sub-sub-band frequency coefficients, resulting in consistent with the frequency of a particular music, and then the introduction of 4Hz clock control for the music beats, and finally through Loudspeakers released.
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Size: 8192 |
Author: lijq |
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Description: CPLD入门知识，老师的课件！希望可以对大家有所帮助。-CPLD Starter knowledge, the teacher s courseware! I hope we can be helpful.
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Size: 1068032 |
Author: 翟进乾 |
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Description: 学习CPLD——FPGA的经过，希望对大家入门有帮助，入了门就好说了，fpga比单片机好无数倍-Learning CPLD- FPGA' s over, we want to help entry, enter the door is like saying, fpga free several times better than the SCM
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Size: 4605952 |
Author: 孙杰 |
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Description: The output frequency requirements for the three waveforms are: the frequency range is adjustable between 20Hz-20kHz; the phase difference between the three waveforms is 120 degrees.
A. of sine wave signal: step 10Hz; frequency stability: better than 1/10000; nonlinear distortion coefficient is less than 3%.
B. of the square wave signal is frequency: the rise and fall time of <1 s;
The requirements of C. for triangular wave signals are that the signal frequency range is adjustable between 20Hz-20kHz.
D. for the above three frequencies are required: the frequency can be preset; when the load is 600, the output signal amplitude is greater than 3V; the output signal amplitude can be adjusted in the range of 100mv~3V, the step length is 100mV.
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Size: 360448 |
Author: 东京的樱花飘过巴黎
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