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[VHDL-FPGA-Verilog] aqusition

Description: 此程序用于视频采集过程中CPLD对时序的转换与组合代码，每两行采集一行，两列采集一列，减小数据量，同时能保证采集完整的一幅图像（输出OUT用于DSP或者单片机中断）-err
Platform: | Size: 1024 | Author: 王强强 | Hits:

[VHDL-FPGA-Verilog] xilinx_design_flow

Description: Xilinx Design Flow Device capabilities are worthless if you can’t use them in YOUR course • Design software should support all ranges of designs from CPLD to the high-density FPGA • Works with YOUR design flow – minimize impacts to the design cycle – work with the tools you already own-Xilinx Design Flow Device capabilities are worthless if you can’t use them in YOUR course • Design software should support all ranges of designs from CPLD to the high-density FPGA • Works with YOUR design flow – minimize impacts to the design cycle – work with the tools you already own
Platform: | Size: 345088 | Author: alex | Hits:

[SCM] lcd

Description: 这是cpld，EPM240驱动lcd的程序，希望与大家分享-This is cpld, EPM240 driver lcd of the procedure, hoping to share with you
Platform: | Size: 1185792 | Author: 蓝风 | Hits:

[VHDL-FPGA-Verilog] CPLD-FPGA-project-doesnt-fit

Description: CPLD/FPGA编译时提示“project doesn t fit! do you wish to override some existing settings and/or assignments？解决方法-CPLD/FPGA编译时提示“project doesn t fit! do you wish to override some existing settings and/or assignments？”
Platform: | Size: 472064 | Author: 李文强 | Hits:

[VHDL-FPGA-Verilog] abc

Description: 时钟频率计,能够实现分频的功能，在CPLD上可以看到所想要的现象-clock frequency ，you can learn about how to frequency and hnow tackle simlar problem,what s more ,you can learn some useful information,i belive you do it!after you have read it ,don t spread!thank you!!!
Platform: | Size: 386048 | Author: wangtao | Hits:

[VHDL-FPGA-Verilog] EDAshuzipinlvji

Description: 1）能够测量正弦波、三角波、锯齿波、矩形波等周期性信号的频率； 2）能直接用十进制数字显示测得的频率； 3）频率测量范围：1HZ~10KHZ切量程能自动切换； 4）输入信号幅度范围为0.5~5V，要求一起自动适应； 5）测量时间：T〈=1.5S；6）用CPLD/FPGA可编程逻辑器件实现 -1) capable of measuring the frequency of the sine wave, triangle wave, sawtooth wave, rectangular wave periodic signal 2) the direct use of decimal digits to display the measured frequency 3) Frequency measuring range: 1HZ ~ 10KHZ cut range can be automatically switched a) input signal amplitude range of 0.5 ~~ 5V requirements with automatic adaptation 5) Measurement time: T < = 1.5S 6) CPLD/FPGA programmable logic devices
Platform: | Size: 882688 | Author: 安德森 | Hits:

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