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[Other] VHDL-FPGA-clock

Description: ＦＰＧＡ数字钟的设计，用VHDL语言编程，max+plus仿真，可在实际电路中验证-FPGA design, VHDL programming, max plus simulation, in the actual circuit verification
Platform: | Size: 269312 | Author: 王越 | Hits:

[Windows Develop] cpu-maxplus

Description: MaxplusII编写的简易cpu，可实现简单加减法等操作-MaxplusII summary prepared by the cpu can realize simple addition and subtraction, etc
Platform: | Size: 513024 | Author: godtroop | Hits:

[VHDL-FPGA-Verilog] MyCPU16

Description: 16位cpu设计VHDL源码，其中包括alu，clock，memory等部分的设计-16 cpu design VHDL source code, including alu, clock, memory and other parts of the design
Platform: | Size: 1089536 | Author: 孙冰 | Hits:

[Embeded-SCM Develop] mips

Description: 在maxplus上实现了一个5级流水线的mips cpu，含cache-In maxplus to achieve a 5-stage pipeline of the mips cpu, with cache
Platform: | Size: 449536 | Author: tong tong | Hits:

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