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Description: 串口的仿真功能 完全支持 单步不支持
串口中断 用户可以使用 用户不能使用
定时器2 不占用 使用
P0,P2 口仿真 完全仿真 只能用作总线
89C52等嵌入式CPU仿真 支持 不支持
系统使用CPU 双CPU设计 单CPU
占用用户堆栈 2个字节 6个字节
I/O引脚占用 一条(p3.5) 两条(p3.0,p3.
-the simulation function fully supports single-step support interrupt users can use user can use timer 2 the use of off-P0 I fully P2 simulation simulation will only be used for bus and other embedded 89C52 CPU simulation support system does not support the use of CP U dual CPU design single CPU utilization users byte stack two six-byte I / O pins occupy a (p3.5) 2 (p3.0, p3.
Platform: |
Size: 6554 |
Author: qjh7651 |
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Description: 很全的中断手册。
INT 00 - CPU-generated - DIVIDE ERROR
INT 01 - CPU-generated - SINGLE STEP (80386+) - DEBUGGING EXCEPTIONS
INT 02 - external hardware - NON-MASKABLE INTERRUPT
INT 03 - CPU-generated - BREAKPOINT
INT 04 - CPU-generated - INTO DETECTED OVERFLOW
INT 05 - PRINT SCREEN CPU-generated (80186+) - BOUND RANGE EXCEEDED
INT 06 - CPU-generated (80286+) - INVALID OPCODE
INT 07 - CPU-generated (80286+) - PROCESSOR EXTENSION NOT AVAILABLE
INT 08 - IRQ0 - SYSTEM TIMER CPU-generated (80286+)
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Platform: |
Size: 3543824 |
Author: 天雨 |
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Description: 串口的仿真功能 完全支持 单步不支持
串口中断 用户可以使用 用户不能使用
定时器2 不占用 使用
P0,P2 口仿真 完全仿真 只能用作总线
89C52等嵌入式CPU仿真 支持 不支持
系统使用CPU 双CPU设计 单CPU
占用用户堆栈 2个字节 6个字节
I/O引脚占用 一条(p3.5) 两条(p3.0,p3.
-the simulation function fully supports single-step support interrupt users can use user can use timer 2 the use of off-P0 I fully P2 simulation simulation will only be used for bus and other embedded 89C52 CPU simulation support system does not support the use of CP U dual CPU design single CPU utilization users byte stack two six-byte I/O pins occupy a (p3.5) 2 (p3.0, p3.
Platform: |
Size: 6144 |
Author: qjh7651 |
Hits:
Description: 很全的中断手册。
INT 00 - CPU-generated - DIVIDE ERROR
INT 01 - CPU-generated - SINGLE STEP (80386+) - DEBUGGING EXCEPTIONS
INT 02 - external hardware - NON-MASKABLE INTERRUPT
INT 03 - CPU-generated - BREAKPOINT
INT 04 - CPU-generated - INTO DETECTED OVERFLOW
INT 05 - PRINT SCREEN CPU-generated (80186+) - BOUND RANGE EXCEEDED
INT 06 - CPU-generated (80286+) - INVALID OPCODE
INT 07 - CPU-generated (80286+) - PROCESSOR EXTENSION NOT AVAILABLE
INT 08 - IRQ0 - SYSTEM TIMER CPU-generated (80286+)
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.-Very wide manual interruption. INT 00- CPU-generated- DIVIDE ERRORINT 01- CPU-generated- SINGLE STEP (80386+)- DEBUGGING EXCEPTIONSINT 02- external hardware- NON-MASKABLE INTERRUPTINT 03- CPU-generated- BREAKPOINTINT 04- CPU-generated- INTO DETECTED OVERFLOWINT 05- PRINT SCREEN CPU-generated (80186+)- BOUND RANGE EXCEEDEDINT 06- CPU-generated (80286+)- INVALID OPCODEINT 07- CPU-generated (80286+)- PROCESSOR EXTENSION NOT AVAILABLEINT 08- IRQ0- SYSTEM TIMER CPU-generated ( 802862B !)...
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Size: 3544064 |
Author: 天雨 |
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Description: java写的一个模拟cpu程序，可以识别汇编程序，支持打印机等外设，界面友好，性能良好，界面是用VE来做的，可以单步执行语句，让你更好地理解cpu内部的工作原理。-write a java simulation cpu procedures, compilation procedures can be identified to support peripherals such as printers, user-friendly, performance, good interface to do with the VE, you can single-step statement, allows you to better understand the working principle of the internal cpu .
Platform: |
Size: 182272 |
Author: spring |
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Description: 用VC++模拟单周期cpu，是体系结构课程的一次作业，包括硬件设计，指令设计等，仅十几条汇编指令啦，程序还支持堆栈操作，能进行算术运算，输入运算表达式就能自动生成汇编代码，代码装载后可以调试运行，支持单步和全速运行-Using VC++ simulation of single-cycle cpu, is a one-stop course architecture, including hardware design, instruction design, only dozens of assembly instructions啦, the program also supports stack operations can be arithmetic, enter the operator expression can be automatic generation of assembly code, the code can be loaded after the commissioning, operation, support single-step and full speed operation
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Size: 403456 |
Author: VC模拟单周期CPU |
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Description: 运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。-Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.
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Size: 822272 |
Author: wang |
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