Search - crc 16 verilog

[Other resource] crc

Description: 用Verilog编写crc校验码，包括8位，12位，16位，32位，非常实用
Platform: | Size: 11138 | Author: asd | Hits:

Description: 循环冗余校验，crc_16,主要运用在数字通信系统。用Verilog HDL编写。-Cyclic Redundancy Check, crc_16, mainly used in digital communications systems. Prepared with Verilog HDL.
Platform: | Size: 31744 | Author: 李鹏 | Hits:

[Communication] crc上传程序

Description: 写CRC编解码程序时，整理的文件，压缩文件既有理论说明，也有源代码。源代码格式用C,VHDL,Verilog。-write CRC codec procedures, collating documents, compressed files both theoretical statements, and the active code. Source code format C, VHDL, Verilog.
Platform: | Size: 706560 | Author: cdl | Hits:

[VHDL-FPGA-Verilog] pcm_verilog

Description: 这是PCM电话传输系统模型的verilog程序,是一个modlesim开发环境下的工程文件,并有波形仿真结果.-PCM telephone transmission system Verilog model of procedures is a modlesim development environment under the project documents, and a waveform simulation results.
Platform: | Size: 47104 | Author: way | Hits:

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: crc校验，非常好用，是从Xilinx的IP演化来的-crc脨拢脩茅拢卢脟鲁拢潞脙脫脙拢卢脢脟
Platform: | Size: 10240 | Author: zl | Hits:

[VHDL-FPGA-Verilog] crc

Description: 用Verilog编写crc校验码，包括8位，12位，16位，32位，非常实用-Prepared using Verilog CRC check codes, including 8, 12, 16, 32, a very practical
Platform: | Size: 11264 | Author: asd | Hits:

[VHDL-FPGA-Verilog] crccode

Description: CRC循环冗余检验 Verilog 编码程序-CRC cyclic redundancy test Verilog coding procedures
Platform: | Size: 1024 | Author: yuanxiaonan | Hits:

[Communication] crc_verilog

Description: HDLC控制协议中CRC校验码算法代码，为CRC16，Verilog语言-HDLC Control Protocol Code in the CRC checksum algorithm code for CRC16, Verilog language
Platform: | Size: 1024 | Author: 刘彻 | Hits:

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: 这是一个在FPGA上实现CRC算法的程序，包含了CRC-8,CRC-12,CRC-16,CRC-CCIT,CRC-32一共五种校验形式。-err
Platform: | Size: 10240 | Author: 李奥运 | Hits:

[Crack Hack] A-PAINLESS-GUIDE-TO-CRC-ERROR-DETECTION-ALGORITHMS

Description: A PAINLESS GUIDE TO CRC ERROR DETECTION ALGORITHMS CRC校验理论与实践的经典教程，Ross写的。-A PAINLESS GUIDE TO CRC ERROR DETECTION ALGORITHMS CRC checksum of the classic theory and practice tutorials, Ross wrote.
Platform: | Size: 184320 | Author: haoz | Hits:

[Communication] crc_check

Description: CRC校验，包括crc8_4、crc12_4、crc16_8、crc32_8-CRC checksum, including crc8_4, crc12_4, crc16_8, crc32_8
Platform: | Size: 4096 | Author: wl | Hits:

[Crack Hack] crc16

Description: 16bit CRC for 8bits data
Platform: | Size: 1024 | Author: 苗淼 | Hits:

[VHDL-FPGA-Verilog] crc

Description: CRC-16 VHDL Source Code
Platform: | Size: 164864 | Author: kobin | Hits:

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: CRC,对于研究通信的有重要意义.利用VERILOG实现8位，16位等CRC原理,-CRC, the study of communication are important. VERILOG to achieve the use of 8, 16, such as CRC principle,
Platform: | Size: 10240 | Author: | Hits:

[matlab] RFC_1622_CRC16_m

Description: RFC1662 CRC-16 table generation and CRC checking. Implemented in embedded matlab with script to test and enable c/c++ code generation. Useful fo check against VHDL/Verilog and other embedded systems to help generate test vectors.
Platform: | Size: 1024 | Author: spaander | Hits:

[VHDL-FPGA-Verilog] Perl_for_CRC

Description: Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8, CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32), any polynomial, and any data input width.-Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex ™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8 , CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32 ), any polynomial, and any data input width.
Platform: | Size: 90112 | Author: 尤恺元 | Hits:

[VHDL-FPGA-Verilog] CRC

Description: CRC校验参考设计Verilog代码,crc8,16,32bit- crc8_8.v : CRC-8, 8-bit data input. crc12_4.v : CRC-12, 4-bit data input. crc16_8.v : CRC-16, 8-bit data input. crc_ccit_8.v : CRC-CCIT, 8-bit data input. crc32_8.v : CRC-32, 8-bit data input.
Platform: | Size: 10240 | Author: guangngqiang | Hits:

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: 包括下面文档： readme.txt : This file crc8_8.v : CRC-8, 8-bit data input. crc12_4.v : CRC-12, 4-bit data input. crc16_8.v : CRC-16, 8-bit data input. crc_ccit_8.v : CRC-CCIT, 8-bit data input. crc32_8.v : CRC-32, 8-bit data input. crcgen.pl : Perl script used to generate Verilog Source for CRC caluculation.(Contains the following files readme.txt : This file crc8_8.v : CRC-8, 8-bit data input. crc12_4.v : CRC-12, 4-bit data input. crc16_8.v : CRC-16, 8-bit data input. crc_ccit_8.v : CRC-CCIT, 8-bit data input. crc32_8.v : CRC-32, 8-bit data input. crcgen.pl : Perl script used to generate Verilog Source for CRC caluculation.)
Platform: | Size: 10240 | Author: chris_lj | Hits:

[VHDL-FPGA-Verilog] Verilog的135个经典设计实例

Description: Verilog的135个经典设计实例，部分摘录如下：【例 9.23】可变模加法/减法计数器【例 11.7】自动售饮料机【例 11.6】“梁祝”乐曲演奏电路【例 11.5】交通灯控制器【例 11.2】4 位数字频率计控制模块【例 11.1】数字跑表【例 9.26】256×16 RAM 块【例 9.27】4 位串并转换器【例 11.8】多功能数字钟【例 11.9】电话计费器程序【例 12.13】CRC 编码【例 12.12】（7，4）循环码纠错译码器【例 12.10】（7，4）线性分组码译码器【例 12.7】11 阶FIR 数字滤波器。。。。。。。(135 classic examples of Verilog design)
Platform: | Size: 167936 | Author: 三棵树机务段 | Hits:

[VHDL-FPGA-Verilog] crc16

Description: verilog 语言下的硬件CRC校验：CRC16(CRC verification in Verilog: CRC 16)
Platform: | Size: 3072 | Author: suncrystal | Hits:

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[Other resource] crc

[VHDL-FPGA-Verilog] crc_16

[Communication] crc上传程序

[VHDL-FPGA-Verilog] pcm_verilog

[VHDL-FPGA-Verilog] crc_verilog_xilinx

[VHDL-FPGA-Verilog] crc

[VHDL-FPGA-Verilog] crccode

[Communication] crc_verilog

[VHDL-FPGA-Verilog] crc_verilog_xilinx

[Crack Hack] A-PAINLESS-GUIDE-TO-CRC-ERROR-DETECTION-ALGORITHMS

[Communication] crc_check

[Crack Hack] crc16

[VHDL-FPGA-Verilog] crc

[VHDL-FPGA-Verilog] crc_verilog_xilinx

[matlab] RFC_1622_CRC16_m

[VHDL-FPGA-Verilog] Perl_for_CRC

[VHDL-FPGA-Verilog] CRC

[VHDL-FPGA-Verilog] crc_verilog_xilinx

[VHDL-FPGA-Verilog] Verilog的135个经典设计实例

[VHDL-FPGA-Verilog] crc16

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