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[Embeded-SCM Develop] 卷积码、CRC

Description: 卷积码的C源程序，包括编码器和译码器。 还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
Platform: | Size: 6144 | Author: 潘华林 | Hits:

[SCM] crc 51

Description: 51单片机的CRC程序，此程序是通过查表的办法进行计算，对于51单片机相当适用-51 SCM CRC procedure, this procedure is through the look-up table approach, for quite applicable MCU 51
Platform: | Size: 3072 | Author: 郭子旺 | Hits:

[Communication] crc上传程序

Description: 写CRC编解码程序时，整理的文件，压缩文件既有理论说明，也有源代码。源代码格式用C,VHDL,Verilog。-write CRC codec procedures, collating documents, compressed files both theoretical statements, and the active code. Source code format C, VHDL, Verilog.
Platform: | Size: 706560 | Author: cdl | Hits:

[Crack Hack] crc

Description: 此源代码实现了CRC5和CRC16的校验以及校验码的产生，可以直接用于RFID标签数字电路。-This source code CRC5 and realize the CRC16 checksum and the emergence of parity-check codes, RFID tags can be directly used for digital circuits.
Platform: | Size: 2048 | Author: 朱秋玲 | Hits:

[Communication] CRC16_D8.v

Description: 完成ccitt crc的校验。针对hdlc协议控制器编写的crc校验模块。通过了仿真测试-Ccitt crc checksum completed. HDLC protocol controller for the preparation of the CRC checksum module. Through the simulation test
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] crccode

Description: CRC循环冗余检验 Verilog 编码程序-CRC cyclic redundancy test Verilog coding procedures
Platform: | Size: 1024 | Author: yuanxiaonan | Hits:

[Other Embeded program] crc16

Description: 16位的CRC校验函数包。符合ccitt标准，查表法校验，速度快。节省CPU时间。值得一看！-16 The CRC checksum function package. Consistent with the CCITT standards, look-up table method validation, fast. Save CPU time. Worth a visit!
Platform: | Size: 1024 | Author: cumt | Hits:

[Crack Hack] crc

Description: 基于FPGA的crc设计，有一定的参考价值，写的比较详细-CRC FPGA-based design, has a certain reference value, a more detailed written
Platform: | Size: 18432 | Author: qlg | Hits:

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: 这是一个在FPGA上实现CRC算法的程序，包含了CRC-8,CRC-12,CRC-16,CRC-CCIT,CRC-32一共五种校验形式。-err
Platform: | Size: 10240 | Author: 李奥运 | Hits:

[VHDL-FPGA-Verilog] crcm

Description: crc 校验，vhdl源码，经仿真能正常运行，供大家参考-CRC checksum, vhdl source, the simulation can be normal operation, for your reference
Platform: | Size: 1024 | Author: fangliang | Hits:

[VHDL-FPGA-Verilog] CRC16bits

Description: 16bit crc encoder ande demo
Platform: | Size: 167936 | Author: chen | Hits:

[Communication] crc_check

Description: CRC校验，包括crc8_4、crc12_4、crc16_8、crc32_8-CRC checksum, including crc8_4, crc12_4, crc16_8, crc32_8
Platform: | Size: 4096 | Author: wl | Hits:

[Crack Hack] crc16

Description: 16bit CRC for 8bits data
Platform: | Size: 1024 | Author: 苗淼 | Hits:

[Software Engineering] CRC

Description: 　本文提出一种通用的CRC 并行计算原理及实现方法,适于不同的CRC 生成多项式和不同并行度(如8 位、16 位、及32 位等) ,与目前已采用的查表法比较,不需要存放余数表的高速存储器,减少了时延,且可通过增加并 行度来降低高速数传系统的CRC 运算时钟频率.-In this paper, a universal principle of CRC and implementation of parallel computing methods for generating different CRC polynomial and different degree of parallelism (eg, 8, 16, and 32-bit, etc.), with the current look-up table method has been used in comparison do not store more than a few tables, high-speed memory, reducing latency, and degree of parallelism can be increased to reduce the high-speed data-transmission system clock frequency of the CRC computation.
Platform: | Size: 144384 | Author: 黑月 | Hits:

[VHDL-FPGA-Verilog] crc

Description: CRC-16 VHDL Source Code
Platform: | Size: 164864 | Author: kobin | Hits:

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: CRC,对于研究通信的有重要意义.利用VERILOG实现8位，16位等CRC原理,-CRC, the study of communication are important. VERILOG to achieve the use of 8, 16, such as CRC principle,
Platform: | Size: 10240 | Author: | Hits:

[Crack Hack] Crc_Parallel

Description: CCITT Parallel CRC 16-bit
Platform: | Size: 1024 | Author: timngo | Hits:

[VHDL-FPGA-Verilog] trunk-hdlc

Description: 高级链路层协议的实现，vhdl，fpga-- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern is assumed only after the end of a frame which is signaled by an abort signal - Zero insertion - Abort pattern generation and checking - Address insertion and detection by software - CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used) - FIFO buffers and synchronization (External) - Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted) - Q.921, LAPB and LAPD compliant. - For complete specifications refer to spec document
Platform: | Size: 188416 | Author: | Hits:

[VHDL-FPGA-Verilog] PCK_CRC16_D1

Description: CRC源代码，VHDL文件，可供参考，16位的-CRC source code, VHDL files, for reference, 16-bit
Platform: | Size: 1024 | Author: ly | Hits:

[VHDL-FPGA-Verilog] CRC-Parallel-Computation

Description: 用软件实现CRC校验码计算很难满足高速数据通信的要求， 基于硬件的实现方法中， 有串行经典算法LFSR,电路以及由软件算法推导出来的其它各种并行计算方法。以经典的LFSR,电路为基础， 研究了按字节并行计算CRC校验码的原理.-Implemented in software CRC checksum calculation is difficult to meet the requirements of high-speed data communications, hardware-based implementations, there are classic serial algorithm LFSR, circuits and software algorithms derived from the other kinds of parallel computing. To the classic LFSR, circuit-based, study by the CRC byte parallel computing principles.
Platform: | Size: 205824 | Author: Geer | Hits:
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