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[Other resource] crc_verilog_xilinx

Description: CRC校验码，用于对数据流进行crc校验。 主要有CRC_16,CRC_8,CRC_32校验。 所用语言为Verilog HDL.-CRC code for the data flow crc check. Main CRC_16, CRC_8, CRC_32 check. The language used for Verilog HDL.
Platform: | Size: 10947 | Author: 李鹏 | Hits:

[Other resource] CRC-Verilog

Description: 此是进行循环冗余效验的Verilog编码，适合多种标准，如CRC16-this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY
Platform: | Size: 3800 | Author: 藏瑞 | Hits:

[VHDL-FPGA-Verilog] crc_verilog_xilinx

Description: CRC校验码，用于对数据流进行crc校验。 主要有CRC_16,CRC_8,CRC_32校验。 所用语言为Verilog HDL.-CRC code for the data flow crc check. Main CRC_16, CRC_8, CRC_32 check. The language used for Verilog HDL.
Platform: | Size: 10240 | Author: 李鹏 | Hits:

[VHDL-FPGA-Verilog] verilog100

Description: 有很多例子及测试代码，对初学者很有帮助，很容易上手-a lot of examples and test code, useful for beginners, it is easy to get started
Platform: | Size: 175104 | Author: bobodu | Hits:

[VHDL-FPGA-Verilog] CRC-Verilog

Description: 此是进行循环冗余效验的Verilog编码，适合多种标准，如CRC16-this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY
Platform: | Size: 3072 | Author: 藏瑞 | Hits:

[VHDL-FPGA-Verilog] Serial_CRC

Description: CRC校验串行实现方法,verilog源码,利用反馈线性移位寄存器的方法,实现简单,适用于串行通信协议中的CRC校验.-CRC checksum method of serial realize, verilog source code, the use of linear feedback shift register method, the realization of simple serial communication protocol for the CRC checksum.
Platform: | Size: 1024 | Author: 徐亮 | Hits:

[Communication] crc_verilog

Description: HDLC控制协议中CRC校验码算法代码，为CRC16，Verilog语言-HDLC Control Protocol Code in the CRC checksum algorithm code for CRC16, Verilog language
Platform: | Size: 1024 | Author: 刘彻 | Hits:

[VHDL-FPGA-Verilog] ethernet.tar

Description: 以太网的vhdl和verilog代码，供大家学习-Ethernet VHDL and Verilog code for everyone to learn
Platform: | Size: 934912 | Author: sunlee | Hits:

[Crack Hack] crc1

Description: CRC编码verilog代码，用于实现crc编码功能-CRC coding Verilog code for CRC encoding capabilities to achieve
Platform: | Size: 1024 | Author: 龙一 | Hits:

[Crack Hack] crc16

Description: 16bit CRC for 8bits data
Platform: | Size: 1024 | Author: 苗淼 | Hits:

[Communication-Mobile] crc32_4

Description: 实现了crc功能的verilog源程序。可以综合。-verilog code for crc
Platform: | Size: 1024 | Author: tree | Hits:

[VHDL-FPGA-Verilog] crc-gen

Description: CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible
Platform: | Size: 60416 | Author: badfox | Hits:

[VHDL-FPGA-Verilog] CRC

Description: CRC校验参考设计Verilog代码 包括所有代码-Verilog code for CRC check reference design includes all the code
Platform: | Size: 10240 | Author: xuzunlei | Hits:

[VHDL-FPGA-Verilog] crc-gen[1]

Description: hamminag code using verilog this code is desinged for detecting
Platform: | Size: 60416 | Author: kim | Hits:

[VHDL-FPGA-Verilog] Perl_for_CRC

Description: Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8, CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32), any polynomial, and any data input width.-Cyclic Redundancy Check (CRC) is an error-checking code that is widely used in data communication systems and other serial data transmission systems. CRC is based on polynomial manipulations using modulo arithmetic. Some of the common Cyclic Redundancy Check standards are CRC-8, CRC-12, CRC-16, CRC-32, and CRC-CCIT. This application note discusses the implementation of an IEEE 802.3 CRC in a Virtex ™ device. The reference design provided with this application note provides Verilog point solutions for CRC-8 , CRC-12, CRC-16, and CRC-32. The Perl script (crcgen.pl) used to generate this code is also included. The script generates Verilog source for CRC circuitry of any width (8, 12, 16, 32 ), any polynomial, and any data input width.
Platform: | Size: 90112 | Author: 尤恺元 | Hits:

[VHDL-FPGA-Verilog] CRC

Description: 用VERILOG语言实现的CRC循环冗余校验码，已成功用于实际项目。-With VERILOG language of the CRC cyclic redundancy check code has been successfully used for actual projects.
Platform: | Size: 484352 | Author: zyb | Hits:

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