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[Embeded-SCM Develop] tdm_hdlc

Description: 在大型通信系统（机架插板式）中多块单板通过TDM总线，利用HDLC协议实现内部通讯的源码-in large communication system (Plug-rack), plus veneer through TDM bus, HDLC protocol using internal communications FOSS
Platform: | Size: 113664 | Author: hubinglong | Hits:

[source in ebook] HDLC

Description: HDLC链路层协议的CRC校验.HDLC使用16位CRC校验。使用的多项式是：x16+x12+x5+x0-HDLC link layer protocol of the CRC checksum. HDLC using 16-bit CRC checksum. Polynomial is used: x16+ X12+ X5+ X0
Platform: | Size: 1024 | Author: 李洪臣 | Hits:

[ARM-PowerPC-ColdFire-MIPS] crc16_8bit.v

Description: 利用verilog硬件描述语言编写的8为并行输入的常crc校验模块。hdlc子模块-Using Verilog hardware description language for the parallel importation of 8 regular CRC checksum module. HDLC sub-modules
Platform: | Size: 1024 | Author: 张纪强 | Hits:

[Communication] crc_verilog

Description: HDLC控制协议中CRC校验码算法代码，为CRC16，Verilog语言-HDLC Control Protocol Code in the CRC checksum algorithm code for CRC16, Verilog language
Platform: | Size: 1024 | Author: 刘彻 | Hits:

[ARM-PowerPC-ColdFire-MIPS] HDLC_crc

Description: 与地铁牵引系统通信的HDLC数据的CRC程序-Communication with the MTR traction system HDLC data CRC program
Platform: | Size: 2048 | Author: 文梁 | Hits:

[VHDL-FPGA-Verilog] hdlc_latest[1]

Description: HDLC解码控制，包括CRC校验，可以在一片3400A FPGA上实现8解码-HDLC decoding control, including the CRC check can be realized in a 3400A FPGA 8 decoding
Platform: | Size: 573440 | Author: 宋珂 | Hits:

[VHDL-FPGA-Verilog] hdlc_rs

Description: 一种带有CRC校验、一次可连续发送1－15块16字节数据、带有曼彻斯特码的hdlc收发程序，在Altera中仿真并在实际芯片中试验过的程序-One kind with a CRC check, send a continuous block of 16 bytes of data 1-15, with Manchester' s hdlc receive procedures in the Altera chip simulation and tested in the actual process
Platform: | Size: 6144 | Author: 周宽裕 | Hits:

[VHDL-FPGA-Verilog] HDLC

Description: verilog HDL语言编写的HDLC协议的IP核，包括通讯控制及CRC。-written in verilog HDL HDLC protocol IP core, including communications control and CRC.
Platform: | Size: 69632 | Author: 王强 | Hits:

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