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[VHDL-FPGA-Verilog] MAC_4_CSA

Description: MAC-4bit verilog source code with CSA style
Platform: | Size: 2048 | Author: bulbul1225 | Hits:

[Crack Hack] TS_Process_V1.0

Description: DVB 加扰软件，对TS流文件进行加扰，符合DVB标准-it s a dvb scramble software . it can scrambling ts stream file ,which apply for dvb standards
Platform: | Size: 80896 | Author: 19869142 | Hits:

[Program doc] csa

Description: This common interview question ask about verilog-This is common interview question ask about verilog
Platform: | Size: 10240 | Author: Hank | Hits:

[VHDL-FPGA-Verilog] csa_verilog_rtl

Description: CSA加扰算法verilog实现，代码经过fpga验证，可以正确实现该算法。-CSA verilog rtl codeing
Platform: | Size: 34816 | Author: he | Hits:

[Software Engineering] csaaa

Description: csa 16 bit verilog code with less delay
Platform: | Size: 62464 | Author: raja | Hits:

[VHDL-FPGA-Verilog] CSA.tar

Description: A Carry Select Adder.
Platform: | Size: 10240 | Author: ax3ghazy | Hits:

[VHDL-FPGA-Verilog] 32-bit new csa adder verilog code

Description: 32-bit new carry select adder verilog code
Platform: | Size: 1236 | Author: gsrwork2017@gmail.com | Hits:

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