Search - cyclone ii D

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[VHDL-FPGA-Verilog] Audio_DAC_FIFO DL : 0: altera的ip核，在sopcbuilder中添加后，在niosII IDE中可以用一条语句实现，音频解码的输出。-altera
Update : 2025-02-17 Size : 15kb Publisher : 朱峰
[Other] Cyclone_II_FPGA_sch DL : 0: altera 飓风二代开发板的原理图，pdf格式 -altera hurricane of the second generation development board schematics, pdf format
Update : 2025-02-17 Size : 231kb Publisher : dansen
[Software Engineering] Cyclone_II_EP2C35_DSP DL : 0: fpga开发板原理图，参考使用，请下载研究-FPGA development board schematics, use and reference, please download study
Update : 2025-02-17 Size : 1.21mb Publisher : ltlt
[VHDL-FPGA-Verilog] dwn_sampler DL : 0: Multirate digital signal processing system which includes sampling rate conversion. This technique is necessary for systems with different input and output sampling rates, as the proposed multirate device is downsampler FPGA implementation of the same is presented. The FPGA synthesis results are verified and report is presented. In order to build down sampler consisting of D F/F and clock generator, are downloaded on cyclone-II FPGA-Multirate digital signal processing system which includes sampling rate conversion. This technique is necessary for systems with different input and output sampling rates, as the proposed multirate device is downsampler FPGA implementation of the same is presented. The FPGA synthesis results are verified and report is presented. In order to build down sampler consisting of D F/F and clock generator, are downloaded on cyclone-II FPGA
Update : 2025-02-17 Size : 2kb Publisher : Mohan Reddy