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[Software Engineering] DC-RM_B-2008.09

Description: synopsys dc_shell 用户手册-reference manual of synopsys dc_shell
Platform: | Size: 41984 | Author: steven | Hits:

[VHDL-FPGA-Verilog] IC035os142_max_worsecase

Description: 数字电路设计，基本单元逻辑综合库，Worsst case 高温慢速条件库，可用dc_shell 环境下调用进行RTL综合。-Digital circuit design, the basic unit logic synthesis libraries, Worsst case conditions of high temperature slow libraries, available dc_shell environment called for RTL synthesis.
Platform: | Size: 5177344 | Author: Ou | Hits:

[VHDL-FPGA-Verilog] IC035os142_min_bestcase

Description: 数字电路设计，基本单元逻辑综合库，Worsst case 低温高速条件库，可用dc_shell 环境下调用进行RTL综合。-Digital circuit design, the basic unit logic synthesis libraries, Worsst case conditions of high temperature slow libraries, available dc_shell environment called for RTL synthesis.
Platform: | Size: 4958208 | Author: Ou | Hits:

[VHDL-FPGA-Verilog] IC035os142_typ

Description: 数字电路设计，基本单元逻辑综合库，Worsst case 室温典型速条件库，可用dc_shell 环境下调用进行RTL综合。-Digital circuit design, the basic unit logic synthesis libraries, Worsst case temperature conditions typical speed database available dc_shell environment called for RTL synthesis.
Platform: | Size: 4964352 | Author: Ou | Hits:

[VHDL-FPGA-Verilog] IC035os142_min_minuse

Description: 数字电路设计，基本单元逻辑综合库，Worsst case 负温度，极端条件库，可用dc_shell 环境下调用进行RTL综合。-Digital circuit design, the basic unit logic synthesis libraries, Worsst case negative temperature, extreme conditions, libraries, available dc_shell environment called for RTL synthesis.
Platform: | Size: 5080064 | Author: Ou | Hits:

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