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[VHDL-FPGA-Verilog] an_dcfifo_top_restored

Description: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
Platform: | Size: 928768 | Author: alison | Hits:

[Other] dcfifo_sim_modelsim_ae_gui

Description: dcfifo verilog source code and modelsim simulator.
Platform: | Size: 19456 | Author: zhangbin | Hits:

[VHDL-FPGA-Verilog] dcfifo_design_example

Description: ALTERA发布的内部FIFO读写示例，很有参考价值，对初学者会有一定的帮助-ALTERA' s internal FIFO read and write examples of great reference value, there will be some help for beginners
Platform: | Size: 33792 | Author: 吕飞 | Hits:

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