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[Other resource] asynch_fifo

Description: FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输，已验证，直接可用
Platform: | Size: 1028005 | Author: alison | Hits:

[Other resource] an_dcfifo_top_restored

Description: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。
Platform: | Size: 928622 | Author: alison | Hits:

[VHDL-FPGA-Verilog] asynch_fifo

Description: FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输，已验证，直接可用-FPGA VERILOG using DCFIFO realize cross-clock domain data transfer, has been verified, directly available
Platform: | Size: 1028096 | Author: alison | Hits:

[VHDL-FPGA-Verilog] an_dcfifo_top_restored

Description: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
Platform: | Size: 928768 | Author: alison | Hits:

[Other] dcfifo_sim_modelsim_ae_gui

Description: dcfifo verilog source code and modelsim simulator.
Platform: | Size: 19456 | Author: zhangbin | Hits:

[Other] DCFIFO

Description: DCFIFO 的modelsim仿真工程，已经写好激励，可以直接使用modelsim观察波形-DCFIFO test
Platform: | Size: 27648 | Author: 刘勇 | Hits:

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