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[Other resource] my_dcm

Description: 在xilinx的ISE环境中配置一个DCM组件，可进行查看程序运行的时间。通过串口与终端设备相连
Platform: | Size: 710456 | Author: 张杰 | Hits:

[Documents] ise

Description: xilinx的时序约束实验，通过阅读本文档，你可以用全局时序约束来轻松提高已有的项目的系统时钟频率，同时你还可以用映射后静态时序报告以及布局布线后静态时序报告来分析你的设计性能-Xilinx timing constraints of the experiment, by reading this document, you can use the overall timing constraints to easily enhance existing projects the system clock frequency, at the same time you can also use static timing report after mapping, as well as after placement and routing static timing analysis report to you design performance
Platform: | Size: 271360 | Author: 江巧微 | Hits:

[VHDL-FPGA-Verilog] my_dcm

Description: 在xilinx的ISE环境中配置一个DCM组件，可进行查看程序运行的时间。通过串口与终端设备相连-In the Xilinx ISE environment, configure a DCM components, can view the program is running time. Through the serial port and terminal equipment connected to
Platform: | Size: 710656 | Author: 张杰 | Hits:

[Other] DCM

Description: 关于dcm的教材。教你如何使用dcm。非常值得一看哦-Materials on the DCM. Teach you how to use the dcm. Oh, very much worth a visit
Platform: | Size: 621568 | Author: 刘峰 | Hits:

[VHDL-FPGA-Verilog] BUFG_CLK0_FB_SUBM

Description: xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
Platform: | Size: 1024 | Author: 娃娃 | Hits:

[VHDL-FPGA-Verilog] BUFG_CLKDV_SUBM

Description: xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
Platform: | Size: 1024 | Author: 娃娃 | Hits:

[Documents] DCM

Description: Xilinx公司诸多型号开发版中的一个模块，能够实现1到16次倍频和分频等功能。使用时现在ISE集成开发环境下利用VHDL进行例化。本文档为个人学习总结-Xilinx, a number of models developed version of a module, be able to achieve 1-16 times multiplier and divider functions. ISE now use integrated development environment for the use of VHDL-based cases. This document for personal study and summary
Platform: | Size: 163840 | Author: 张潘睿 | Hits:

[VHDL-FPGA-Verilog] DCM

Description: ISE实现DCM组建例化，得到3倍频时钟-ISE to achieve established cases of DCM, received 3 octave clock
Platform: | Size: 370688 | Author: ll | Hits:

[VHDL-FPGA-Verilog] dcm_40

Description: 基于ISE 的DCM IP 核的一个应用，输入100M，输出40M-One application of DCM IP core in ISE.
Platform: | Size: 269312 | Author: Liu Wei | Hits:

[VHDL-FPGA-Verilog] DCM_12M_1M

Description: xilinx下DCM输出12Mhz和1Mhz-Verilog DCM xilinx ISE
Platform: | Size: 1024 | Author: fpgabo | Hits:

[VHDL-FPGA-Verilog] Xilinx_DCM

Description: 基于ise 10.0来实现Xilinx的时钟设计和管理-Xilinx dcm digital clock manager
Platform: | Size: 8192 | Author: ise_dcm | Hits:

[VHDL-FPGA-Verilog] DCM

Description: 详细介绍了基于XILINX公司FPGA时钟管理模块DCM的IP核生成和使用-xilinx ise DCM
Platform: | Size: 621568 | Author: mawei | Hits:

[VHDL-FPGA-Verilog] dcm_test2

Description: xilinx fpga 倍频的例子，包含整个工程， 如果去用ISE 实现倍频，dcm 用法-xilinx s FPGA dcm example
Platform: | Size: 315392 | Author: 林端 | Hits:

[VHDL-FPGA-Verilog] ledvhd

Description: ISE与VHDL入门程序，使用DCM分频实现LED的控制。-ISE and VHDL entry procedures with DCM divide LED control.
Platform: | Size: 395264 | Author: qinkun | Hits:

[VHDL-FPGA-Verilog] 296517dcm

Description: 基于ISE 12.4的IP 核调用 DCM 其功能是将开发板上的系统时钟变为任意的所需时钟 适合初学者学习-ISE 12.4 IP core based on DCM and its function is to call the board will develop into any desired system clock clock for beginners to learn
Platform: | Size: 269312 | Author: 付神九 | Hits:

[VHDL-FPGA-Verilog] 7_07_DCMSim

Description: 学习使用xilinx的简单例程，熟悉ise平台。DCM 仿真。-xilinx demo code
Platform: | Size: 1432576 | Author: 钱学文 | Hits:

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