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[File Operate] DDR_SDRAM_use_in_embedded DL : 1: 很多嵌入式系统，特别是应用于图像处理与高速数据采集等场合的嵌入式系统，都需要高速缓存大量的数据。DDR（Double Data Rate，双数据速率）SDRAM由于其速度快、容量大，而且价格便宜，因此能够很好地满足上述场合对大量数据缓存的需求。但DDR SDRAM的接口不能直接与现今的微处理器和DSP的存储器接口相连，需要在其间插入控制器实现微处理器或DSP对存储器的控制。-many embedded systems, especially for image processing and high-speed data acquisition, and so on the embedded system, Cache require large amounts of data. DDR (Double Data Rate, double-data rate) SDRAM due to its speed, large capacity, and their prices are cheaper, it can be a very good occasion to meet these massive data cache demand. But DDR SDRAM interface directly with today's microprocessor and DSP memory interface connected, During the need to insert controller microprocessor or DSP memory of the control.
Update : 2008-10-13 Size : 231.98kb Publisher : joucan
[File Format] DDR_SDRAM_use_in_embedded DL : 0: 很多嵌入式系统，特别是应用于图像处理与高速数据采集等场合的嵌入式系统，都需要高速缓存大量的数据。DDR（Double Data Rate，双数据速率）SDRAM由于其速度快、容量大，而且价格便宜，因此能够很好地满足上述场合对大量数据缓存的需求。但DDR SDRAM的接口不能直接与现今的微处理器和DSP的存储器接口相连，需要在其间插入控制器实现微处理器或DSP对存储器的控制。-many embedded systems, especially for image processing and high-speed data acquisition, and so on the embedded system, Cache require large amounts of data. DDR (Double Data Rate, double-data rate) SDRAM due to its speed, large capacity, and their prices are cheaper, it can be a very good occasion to meet these massive data cache demand. But DDR SDRAM interface directly with today's microprocessor and DSP memory interface connected, During the need to insert controller microprocessor or DSP memory of the control.
Update : 2025-02-17 Size : 232kb Publisher : joucan
[VHDL-FPGA-Verilog] c_xapp260 DL : 0: xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Generator to simplify memory interface. This white paper discusses the various memory interface controller design challenges facing Warfare and Xilinx solutions, but also explains how to use Xilinx Software tools and hardware-proven reference designs to be for your own With (from low-cost DDR SDRAM applications to such as 667 Mb/s This higher performance DDR2 SDRAM interface) design a complete deposit Storage device interface solution.
Update : 2025-02-17 Size : 1.07mb Publisher : 陈阳
[VHDL-FPGA-Verilog] ddr2_controller DL : 0: DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.
Update : 2025-02-17 Size : 51kb Publisher : yanxp
[VHDL-FPGA-Verilog] sdram_controller_latest.tar DL : 0: sdram_controller_latest.tar.gz -it is memory DDR controller, but it has 8 bit only data bus wide ,and hasn’t independents clock for source read-write data and ddr + controller size. Wrote on the VHDL language.-sdram_controller_latest.tar.gz -it is memory DDR controller, but it has 8 bit only data bus wide ,and hasn’t independents clock for source read-write data and ddr + controller size. Wrote on the VHDL language.
Update : 2025-02-17 Size : 30kb Publisher : Andrei
[VHDL-FPGA-Verilog] ug230.pdf DL : 0: The Spartan-3E Starter Kit board highlights the unique features of the Spartan-3E FPGA family and provides a convenient development board for embedded processing applications. The board highlights these features: • Spartan-3E FPGA specific features • Parallel NOR Flash configuration • MultiBoot FPGA configuration from Parallel NOR Flash PROM • SPI serial Flash configuration • Embedded development • MicroBlazeTM 32-bit embedded RISC processor • PicoBlazeTM 8-bit embedded controller • DDR memory interfaces
Update : 2025-02-17 Size : 5.58mb Publisher : Akalu Lentiro
[VHDL-FPGA-Verilog] ddr_sdr_latest[1].tar DL : 0: ddr sdram 控制器的接口，为工业标准化存储设备提供简单的接口-The DDR SDRAM Controller provides the user with a simplified interface to industry standard memory devices. Using this controller makes accesses to DDR SDRAM devices as simple as possible.
Update : 2025-02-17 Size : 79kb Publisher : hxr
[Industry research] Design-and-implementation-of-High-Speed-Pipelined DL : 0: Design and implementation of High Speed Pipelined DDR SDRAM memory Controller
Update : 2025-02-17 Size : 754kb Publisher : JAGRUTHI M S
[Software Engineering] ALI_M1621(71) DL : 0: M1671 - P4 Super North Bridge – CPU, AGP, PCI and Memory Controller The M1671 is a high-performance, high-value North Bridge that supports all Pentium 4 processors. With internal 128-bit architecture optimized for CPU bus, DDR and AGP4X interface, the M1671 has outstanding high system performance under all types of system operations. The M1671 also has a complete set of mobile features which makes the M1671 an ideal solution for mobile systems. Pdf Datasheet-M1671 - P4 Super North Bridge – CPU, AGP, PCI and Memory Controller The M1671 is a high-performance, high-value North Bridge that supports all Pentium 4 processors. With internal 128-bit architecture optimized for CPU bus, DDR and AGP4X interface, the M1671 has outstanding high system performance under all types of system operations. The M1671 also has a complete set of mobile features which makes the M1671 an ideal solution for mobile systems. Pdf Datasheet
Update : 2025-02-17 Size : 1.07mb Publisher : serge
[VHDL-FPGA-Verilog] source DL : 0: 2. /qdr2/source/qdr2_io.v > Top level file includes declarations of HSTL1 and LVTTL I/O standards /qdr2/source/qdr2.v > Main module of the QDR memory controller /qdr2/source/pipeline.v > Pipeline module for increasing performance /qdr2/source/oddr_xp.v > Output DDR module /qdr2/source/pll_qdr_sim.v > Pll module for simulation /qdr2/source/pll_qdr_syn.v > Pll module for synthesis /qdr2/source/magma.v- 2. /qdr2/source/qdr2_io.v > Top level file includes declarations of HSTL1 and LVTTL I/O standards /qdr2/source/qdr2.v > Main module of the QDR memory controller /qdr2/source/pipeline.v > Pipeline module for increasing performance /qdr2/source/oddr_xp.v > Output DDR module /qdr2/source/pll_qdr_sim.v > Pll module for simulation /qdr2/source/pll_qdr_syn.v > Pll module for synthesis /qdr2/source/magma.v
Update : 2025-02-17 Size : 16kb Publisher : liuxuemin