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[Other resource] ref-ddr-sdram-vhdl DL : 0: 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
Update : 2008-10-13 Size : 1007.48kb Publisher : 包盛花
[Other resource] ref-sdr-sdram-vhdl DL : 1: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Update : 2008-10-13 Size : 758.44kb Publisher : 张涛
[Other] ref-ddr-sdram-vhdl DL : 0: 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Update : 2008-10-13 Size : 426.81kb Publisher : kevin
[Other Embeded program] DDR SDRAM控制器的VHDL代码已经测试 DL : 0: DDR SDRAM控制器的VHDL代码已经测试
Update : 2011-02-08 Size : 15.1kb Publisher : bbk2000
[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl DL : 0: 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
Update : 2025-02-17 Size : 1007kb Publisher : 包盛花
[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl DL : 0: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Update : 2025-02-17 Size : 758kb Publisher : 张涛
[Other] ref-ddr-sdram-vhdl DL : 0: 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Update : 2025-02-17 Size : 427kb Publisher : kevin
[Documents] SDRAM-VHDL DL : 0: SDRAM控制器的VHDL实现，pdf格式，有需要多的，联系我-SDRAM controller VHDL, pdf format, it needs more, Contact
Update : 2025-02-17 Size : 122kb Publisher :
[VHDL-FPGA-Verilog] DDRSDRAM DL : 0: 基于FPGA 实现DDR SDRAM的控制器-FPGA-based realization of DDR SDRAM controller
Update : 2025-02-17 Size : 463kb Publisher : 张宁
[VHDL-FPGA-Verilog] t26a_ibis DL : 0: ddr sdram 的控制代码，采用VHDL语言书写-ddr sdram control code, the use of VHDL language
Update : 2025-02-17 Size : 275kb Publisher : zxb
[VHDL-FPGA-Verilog] DDR_SDRAM_controller DL : 0: ddr sdram 的vhdl实现，包括各个模块的实现以及仿真文件-ddr sdram realization of VHDL, including the realization of each module as well as the simulation file
Update : 2025-02-17 Size : 998kb Publisher : shroy
[VHDL-FPGA-Verilog] DDR_SDRAM_controller DL : 0: DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O
Update : 2025-02-17 Size : 129kb Publisher : xbl
[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl DL : 0: 基于VHDL编写的DDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the DDR-SDRAM controller programming, is currently the industry s commonly used RAM controller
Update : 2025-02-17 Size : 1007kb Publisher : wfs
[Other] testbench DL : 0: ddr sdram controller datd module source code
Update : 2025-02-17 Size : 3kb Publisher : KrishnaKishore
[VHDL-FPGA-Verilog] DDRSDRAMControllerverilogcode DL : 0: 这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。-This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Front-End FIFOs, DDR SDRAM Controller and Datapath Module. Are one of the main DDR SDRAM Controller, of course, have the test module.
Update : 2025-02-17 Size : 466kb Publisher : fdasfds
[VHDL-FPGA-Verilog] ddr_sdram_controller_vhdl DL : 0: DDR SDRAM控制器的VHDL代码已经测试-DDR SDRAM controller VHDL code
Update : 2025-02-17 Size : 13kb Publisher : tom
[VHDL-FPGA-Verilog] c_xapp851 DL : 1: 这是xilinx应用指南xapp851的中文版本。本应用指南描述了在 Virtex™ -5 器件中实现的 200 MHz DDR SDRAM （JEDEC DDR400 (PC3200) 标准）控制器。本设计实现使用 IDELAY 单元调整读数据时序。读数据时序校准和调整在此控制器中完成。-This is the xilinx application note xapp851 the Chinese version. This application note describes the Virtex ™ -5 devices to achieve 200 MHz DDR SDRAM (JEDEC DDR400 (PC3200) standard) controller. The Design and Implementation of the use of IDELAY unit to adjust read data timing. Reading the data calibration and adjust the timing for completion of this controller.
Update : 2025-02-17 Size : 399kb Publisher : 陈阳
[VHDL-FPGA-Verilog] ddr-sdram DL : 0: DDR SDRAM控制器verilog代码及中文说明文档,对DDR开发很有用的哈。-Verilog source code for DDR SDRAM controler design,including guide book in chinese.
Update : 2025-02-17 Size : 902kb Publisher : runxin
[Software Engineering] SDRAM DL : 0: 连接Nios II 和SDRAM的系统设计，DDR SDRAM设计及调试经验总结，MT48LC16M16资料。-failed to translate
Update : 2025-02-17 Size : 1.82mb Publisher : luyi
[VHDL-FPGA-Verilog] ddr DL : 0: DDR SDRAM 控制器 VHDL代码，可支持32bits数据总线-VHDL code for DDR SDRAM controller, supporting 32bits data bus
Update : 2025-02-17 Size : 9kb Publisher : chen

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