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[Other resource] xapp935

Description: ddr2 controller, verilog source code from xilinx
Platform: | Size: 347004 | Author: Hubert | Hits:

[Other] u26a_spice

Description: ddr2控制器一些源码，控制时序及怎样通过嵌入式cpu来进行控制的实例-ddr2 Controller some source code, and how to control the timing of embedded cpu passed to the control of the examples
Platform: | Size: 297984 | Author: | Hits:

[VHDL-FPGA-Verilog] xapp935

Description: ddr2 controller, verilog source code from xilinx
Platform: | Size: 347136 | Author: Hubert | Hits:

[Compress-Decompress algrithms] DDR2_sdram

Description: DDR2 的控制器，它是由LATTICE的编译器生成。-DDR2 controller, it is by the compiler-generated LATTICE.
Platform: | Size: 966656 | Author: 李国 | Hits:

[VHDL-FPGA-Verilog] vga_control

Description: vga 控制器的verilog 源码 ，fpga上可实现图片的显示-vga controller Verilog source code, fpga achievable picture display
Platform: | Size: 1024 | Author: zys | Hits:

[VHDL-FPGA-Verilog] OpenSPARC_DDR2_controller_RTL_Files

Description: 基于FPGA的DDR2控制程序，用verilog编写的。-FPGA-based DDR2 control procedures, prepared by using Verilog.
Platform: | Size: 30720 | Author: 王头 | Hits:

[VHDL-FPGA-Verilog] Xil3SD1800A_MIG_simplifiedUI_vlog_v92

Description: verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
Platform: | Size: 908288 | Author: ma yirong | Hits:

[VHDL-FPGA-Verilog] ssss

Description: spartan—3a对ddr2读写控制源程序，有verilog和vhdl版本-spartan-3a ddr2 read and write control of the source, there are versions of verilog and vhdl
Platform: | Size: 324608 | Author: 刘一平 | Hits:

[VHDL-FPGA-Verilog] DDRCHv11

Description: Source code for ddr2 dram controller for BEEE
Platform: | Size: 661504 | Author: shiva | Hits:

[VHDL-FPGA-Verilog] ddr2_demo

Description: lattice 操作DDR2控制器verilog源代码-the verilog source code of ddr2 control of lattice
Platform: | Size: 886784 | Author: 肖涛 | Hits:

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