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[Program doc] DDR_MMC_JEDEC

Description: 关于DDR，DDR2,DDR3和MMC的标准规范。-On the DDR, DDR2, DDR3 and the MMC standards.
Platform: | Size: 13941760 | Author: 崔海群 | Hits:

[VHDL-FPGA-Verilog] cntl_ddr3(xilinx)

Description: xilinx ddr3最新VHDL代码,通过调试-xilinx ddr3 latest VHDL code through debugging
Platform: | Size: 101376 | Author: zhang chi | Hits:

[Algorithm] ddr3_mcib_rmbs

Description: DDR3走先得详细规则及注意事项，考虑的等长走线，数据线与地址线、控制线长度关系-DDR3 take detailed rules and precautions come to consider the alignment of equal length, the data line and address lines, control lines the length of the relationship between
Platform: | Size: 2380800 | Author: 孙海洋 | Hits:

[Finance-Stock software system] MT41J64M16LA-187E

Description: Micron DDR3 内存 MT41J64M16LA-187E schlib.-Micron DDR3 MT41J64M16LA-187E symbol lib .
Platform: | Size: 2048 | Author: gao | Hits:

[Software Engineering] DDR_Eye_Patterns

Description: DDR1 DDR2 DDR3眼图分析。本文根据自己设计的DDR“读”“写”分离软件，介绍一种把“读”眼图和“写”眼 图分离开的方法，并创新地引入模板测试的方法。-DDR1 DDR2 DDR3 Eye Patterns
Platform: | Size: 648192 | Author: 邓奇勋 | Hits:

[Software Engineering] ASP_7738G_DDR3

Description: Schematic Diagram for Acer Aspire 7738G DDR3 Laptop.
Platform: | Size: 1895424 | Author: Dinyasoft | Hits:

[VHDL-FPGA-Verilog] software

Description: ddr3 Test program for Altera FPGA Starter Kit
Platform: | Size: 743424 | Author: mil | Hits:

[ARM-PowerPC-ColdFire-MIPS] 52K_19200_1_2010.02.08.16.06.44_4247_KO[1].pdf.zi

Description: DDR3 SDRAM datasheet please refer want to development DDR3 Controller
Platform: | Size: 1479680 | Author: mil | Hits:

[VHDL-FPGA-Verilog] DDR3

Description: DDR3控制器，基于Altera平台，修改管教后直接可以下载进PFGA-DDR3 controller, based on Altera platform, modify the discipline can be downloaded directly into the PFGA
Platform: | Size: 559104 | Author: andy | Hits:

[VHDL-FPGA-Verilog] 94117c05d50c

Description: Its a clock Sequence for DDR3 Controller.Hope u find it useful
Platform: | Size: 13312 | Author: Shab | Hits:

[Software Engineering] sdram_introduce

Description: sdram内存技术指南（sdr,ddr,ddr2,ddr3）-sdram memory technology guide (sdr, ddr, ddr2, ddr3)
Platform: | Size: 4068352 | Author: 杨洪涛 | Hits:

[Software Engineering] origen_s5pv310_ev_baseboard

Description: Samsung S5PV310 Exynos 4210 底板原理图，CORTEX A9，支持DDR3-Samsung S5PV310 Exynos 4210 floor schematics, CORTEX A9, support for DDR3
Platform: | Size: 111616 | Author: 陈风 | Hits:

[VHDL-FPGA-Verilog] ddr3_controller1

Description: ddr3 controller for axi interface
Platform: | Size: 1024 | Author: ashu | Hits:

[VHDL-FPGA-Verilog] DDR3 SDRAM Verilog Model

Description: ddr3的逻辑带么参考，有需要的可以看一下。。。。。。。。。(ddr3 ssscoede code code code)
Platform: | Size: 70656 | Author: sss911 | Hits:

[Other] ddr3

Description: FPGA实现DDR3控制器()
Platform: | Size: 18816000 | Author: freegi | Hits:

[VHDL-FPGA-Verilog] DDR3

Description: spartan6 里使用DDR3IP核，有教程以及源码(spartan6 with ddr3,source and tutorial)
Platform: | Size: 29082624 | Author: 时光隐匿 | Hits:

[VHDL-FPGA-Verilog] DDR3的工作原理

Description: DDR3原理，详细的介绍了DDR3内部结构以及工作原理(DDR3 principle, detailed introduction of the internal structure of DDR3 and the principle of work)
Platform: | Size: 678912 | Author: crizy0703 | Hits:

[Software Engineering] DDR3读写测试

Description: MIG IP控制DDR3读写测试，于MIG IP核用户接口时序较复杂，这里给出扩展接口模块用于进一步简化接口时序。(MIG IP controls DDR3 reading and writing tests, and the time sequence of MIG IP kernel user interface is more complex.)
Platform: | Size: 798720 | Author: 陈先森你好 | Hits:

[VHDL-FPGA-Verilog] XILINX平台DDR3设计教程

Description: 从零开始的Xilinx DDR3 控制程序编写教程，利用MIS IP核通过自编逻辑实现对DDR3的读写，强烈推荐(This is a zero to start Xilinx DDR3 control program written tutorial, the use of MIS IP kernel through the self compiled logic to achieve DDR3 reading and writing, strongly recommended.)
Platform: | Size: 23005184 | Author: 喵卡琳 | Hits:

[assembly language] ddr3

Description: ALINX7010 ddr3读写测试仿真实验官方教程 附说明和代码 Vivado 实现(Alinx7010 DDR3 read write test simulation experiment official course Description and code attached Vivado implementation)
Platform: | Size: 3036160 | Author: 心素如简 | Hits:
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