Search - dds vhdl altera

[Other resource] DDS_VHDL_xzy

Description: 在EDA开发软件QuartusII上利用VHDL语言实现DDS信号发生器，芯片是Altera公司的-in EDA software development QuartusII use VHDL DDS signal generator , chip companies are Altera
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[Communication] Project1-DDS

Description: 直接频率和成DDS，可以在Altera的FPGA下载实现-directly into DDS frequency and can be downloaded from Altera FPGA Implementation
Platform: | Size: 8192 | Author: lf | Hits:

[VHDL-FPGA-Verilog] DDS_VHDL_xzy

[VHDL-FPGA-Verilog] BFSK_VHDL_CODING

Description: 使用DDS技术，应用altera公司的芯片，以及杭州康芯公司的试验箱，实现BFSK信号的调制解调-The use of DDS technology, applications altera chips, as well as the core company in Hangzhou, Culture and Sport chamber, the realization of BFSK signal modulation and demodulation
Platform: | Size: 265216 | Author: 叶峰 | Hits:

[Software Engineering] dds

Description: 基于FPGA的双路可移相任意波形发生器 Altera中国大学生电子设计文章竞赛获奖作品刊登-FPGA-based dual phase shifter can be arbitrary waveform generator Altera China Undergraduate Electronic Design Contest winning entries published articles
Platform: | Size: 1695744 | Author: 姜兆刚 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 使用VHDL硬件描述语言实现了直接频率合成器的制作，并在Altera公司的CycloneII上得到实现，验证了代码的正确性。用户操作可以参照程序中的说明，请使用QuartusII6.0以上版本打开，低版本打开时会有错误提示-Using VHDL hardware description language to achieve a direct frequency synthesizer production, and Altera s CycloneII be realized, to verify the correctness of the code. Users can refer to procedures, please use the above QuartusII6.0 open, low-version will be opened error
Platform: | Size: 105472 | Author: xx | Hits:

[VHDL-FPGA-Verilog] FPGA_signal_general

Description: 摘要：介绍了直接数字频率合成 (DDS) 技术的基本原理，给出了基于Altera公司FPGA器件的一个三相正弦信号发生器的设计方案，同时给出了其软件程序和仿真结果。仿真结果表明：该方法生成的三相正弦信号具有对称性好、波形失真小、频率精度高等优点，且输出频率可调。关键词：直接数字频率合成；现场可编程门阵列；FPGA；三相正弦信号-Abstract: Direct Digital Synthesis (DDS) technology, the basic principles are given Altera-based FPGA devices the company a three-phase sinusoidal signal generator design program, at the same time give its software programs and simulation results. The simulation results show that: the method to generate three-phase sinusoidal signal with good symmetry, waveform distortion small, the frequency of high precision, and adjustable output frequency. Key words: direct digital synthesizer field programmable gate array FPGA three-phase sinusoidal signal
Platform: | Size: 101376 | Author: 赵文 | Hits:

[VHDL-FPGA-Verilog] dds

Description: dds算法的fpga实现 altera 根据不同设置，输出不同频率的信号源-dds algorithm to achieve fpga set according to different altera, the output of the signal source at different frequencies
Platform: | Size: 1086464 | Author: liulei | Hits:

[SCM] ddsdds

Description: 摘要：介绍了直接数字频率合成 (DDS) 技术的基本原理，给出了基于Altera公司FPGA器件的一个三相正弦信号发生器的设计方案，同时给出了其软件程序和仿真结果。仿真结果表明：该方法生成的三相正弦信号具有对称性好、波形失真小、频率精度高等优点，且输出频率可调。关键词：直接数字频率合成；现场可编程门阵列；FPGA；三相正弦信号 (2009-01-04, VHDL, 99KB, 9次) -hgfhtht rrgtsrt rthg rgrswt sgethwrathwtHY TSRTTHSRHGWth rtyhthgrg rgsrg thrsrgsg rgsgrgthsrg
Platform: | Size: 568320 | Author: nbonwenli | Hits:

[VHDL-FPGA-Verilog] DDS

Description: DDS频率合成器（使用VHDL硬件描述语言，通过Altera QuartusII开发）-DDS frequency synthesizer (using VHDL hardware description language, through the development of Altera QuartusII)
Platform: | Size: 233472 | Author: 刘磊 | Hits:

[Other] dds_v3_test3

Description: DDS控制器在FPGA上的实现，使用Quartus II8.1开发环境，使用Altera 原理图设计方法，10位宽度，配合dac9-DDS controller in the FPGA on the realization of Quartus II8.1 use development environment, the use of Altera schematic design, 10-bit width, with dac900
Platform: | Size: 14858240 | Author: 张文 | Hits:

[VHDL-FPGA-Verilog] Study_on_Key_Technologies_of_n4-DQPSK_Modulation_a

Description: 本文首先研究可4一DQPsK调制解调系统中调制部分的基本原理和各个模块的设计方案，重点研究成形滤波器和直接数字频率合成器 (DireetoigitalFrequeneySynihesis，简称DDS)，并针对各个关键模块算法进行matlab设计仿真，展示仿真结果。其次，研究调制解调系统解调部分的基本原理和各个模块的设计方案，重点研究差分解调，数字下变频和位同步算法，也针对其各个关键模块进行算法的Matlab设计仿真。然后用Matlab对整个系统进行理论仿真，得出结论。在此基础上，采用超高速集成电路硬件描述语言(VeryHighspeedxntegatedeireuitHardware DescriptionLan即age，简称VHDL)在Altera公司 Quartusll7.0开发环境下设计并实现各个功能块，通过仿真来证明功能正确性。再次，用 Protel99SE进行印制电路板(Prinicircuitboard，简称PcB)设计，从原理图到封装，再到布局布线。焊接调试完毕后，将设计好的程序下载至FPGA主芯片。最后观察信号时域波形、星座图、眼图。本系统信源输入符号速率100kbPs，调制中频10MHz。测试结果验证系统的正确性，实现了从数字基带到中频的可4一DQPSK调制解调系统-This study is the first 4 1 DQPsK modem modulation system, part of the basic principles and design of each module, focusing on shaping filter and a direct digital frequency synthesizer (DireetoigitalFrequeneySynihesis, referred to as DDS), and to address all the key modules algorithm matlab design simulation to show simulation results. Second, the study of modulation and demodulation system demodulation part of the basic principles and design of each module, focusing on differential demodulation, digital down conversion and bit synchronization algorithm, but also for its various key module of the Matlab algorithm design and simulation. Then use the Matlab simulation of the entire system theory, reach a conclusion. On this basis, , Using ultra-high speed integrated circuit hardware description language (VeryHighspeedxntegatedeireuitHardware DescriptionLan that age, referred to as VHDL) in the Altera Corporation Quartusll7.0 development environment to design and implement the variou
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[Other] ddsgt

Description: 采用DDS技术，在Altera 8.1软件下，利用VHDL语言编程，从而产生正弦波信号，经调试，文件正确可用-Using DDS technology, Altera 8.1 software, using the VHDL language programming, resulting in sine wave signal, after debugging, documentation is available right
Platform: | Size: 241664 | Author: 郭岩伟 | Hits:

[VHDL-FPGA-Verilog] ALTERA@FPGA@example

Description: 基于ALTERA的几个VHDL实例，如FPGA单片机，DDS的正弦信号发生器，FPGA视频监控-VHDL example：such as DDS Sine signal generator
Platform: | Size: 27246592 | Author: bin | Hits:

[Other] DDS

Description: 利用现场可编程逻辑门阵列FPGA实现直接数字频率合成（DDS）的原理，以及以DDS为核心的信号发生器。探讨DDS技术在FPGA中的实现方法，提出采用ALTERA公司的FLEX系列FPGA芯片FLEX10K进行直接数字频率合成的VHDL源程序。-The use of field-programmable gate array FPGA to realize the principle of the direct digital frequency synthesis (DDS) DDS as the core of the signal generator. DDS technology in the FPGA implementation method proposed the FLEX series FPGA chip FLEX10K ALTERA Company VHDL source code for direct digital frequency synthesis.
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[Other resource] DDS_VHDL_xzy

[Communication] Project1-DDS

[VHDL-FPGA-Verilog] DDS_VHDL_xzy

[VHDL-FPGA-Verilog] BFSK_VHDL_CODING

[Software Engineering] dds

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] FPGA_signal_general

[VHDL-FPGA-Verilog] dds

[SCM] ddsdds

[VHDL-FPGA-Verilog] DDS

[Other] dds_v3_test3

[VHDL-FPGA-Verilog] Study_on_Key_Technologies_of_n4-DQPSK_Modulation_a

[Other] ddsgt

[VHDL-FPGA-Verilog] ALTERA@FPGA@example

[Other] DDS

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