Search - dds IP quartus

[VHDL-FPGA-Verilog] DDS

Description: Quartus中实现的DDS 使用的是altera提供的IP core-DDS achieved Quartus using IP core provided by altera
Platform: | Size: 83968 | Author: ray | Hits:

Description: 实现函数波形发生器的功能，内有用自己编的源代码实现的，也有用quartus的IP核实现的。-The realization of the function waveform generator function, useful for their own realization of the source code, it also uses the IP core quartus achieved.
Platform: | Size: 1251328 | Author: bluesky428 | Hits:

[VHDL-FPGA-Verilog] BPSK

Description: 在quartus ii下完成的用VHDL语言编写的数字式调频BPSK的调制，其中DDS和成型滤波使用ip核完成-Accomplished in quartus ii the use of VHDL language digital FM BPSK modulation, which use the ip filter DDS and forming complete nuclear
Platform: | Size: 326656 | Author: | Hits:

[VHDL-FPGA-Verilog] MIF_file_of_Sine_Wave_Generator

Description: 在Quartus的DDS设计中，通常会用到mif或者hex文件存储函数值，被ROM的IP模块调用。本程序是在Matlab环境下，根据所需数据位数和长度自定义mif文件。-Quartus DDS design, usually used in the mif or hex file storage function value, call the ROM of IP modules. This program is in the Matlab environment, according to the desired data bits and the length of custom mif file.
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] DDS

Description: Quartus环境下，使用VHDL语言和IP核进行的通用DDS设计。-Quartus environment, general DDS design using VHDL and IP cores.
Platform: | Size: 1468416 | Author: | Hits:

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[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] BPSK

[VHDL-FPGA-Verilog] MIF_file_of_Sine_Wave_Generator

[VHDL-FPGA-Verilog] DDS

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