Search - dds open

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[Communication-Mobile] EXPT12_10_PHAS_PLL1 DL : 0: VHDL 实现DDS的数字移相信号发生器的设计代码.直接解压打开就可以运行..自己写的代码-VHDL shifter DDS signal generator design code. Directly extract can run on open .. write their own code
Update : 2008-10-13 Size : 117.73kb Publisher : haiou
[Other resource] PhotoshopplusinDDS DL : 1: 一个让photoshop直接支持directX的DDS格式的插件可以在photoshop中直接保存为dx的dds格式不用再打开dx中的工具进行转换-a photoshop direct support for the DDS format directX a plug-in p hotoshop directly to the preservation of dx dds format no longer open dx of conversion tools
Update : 2008-10-13 Size : 182.59kb Publisher : jinghao
[Communication-Mobile] EXPT12_10_PHAS_PLL1 DL : 0: VHDL 实现DDS的数字移相信号发生器的设计代码.直接解压打开就可以运行..自己写的代码-VHDL shifter DDS signal generator design code. Directly extract can run on open .. write their own code
Update : 2025-02-17 Size : 117kb Publisher : haiou
[Game Engine] PhotoshopplusinDDS DL : 0: 一个让photoshop直接支持directX的DDS格式的插件可以在photoshop中直接保存为dx的dds格式不用再打开dx中的工具进行转换-a photoshop direct support for the DDS format directX a plug-in p hotoshop directly to the preservation of dx dds format no longer open dx of conversion tools
Update : 2025-02-17 Size : 182kb Publisher : jinghao
[SCM] dds DL : 0: 基于ATMEGA16和DDS的信号发生器的代码，内含一个基于IAR集成开发环境的工程，可直接用IAR打开，编译并烧入单片机，是本人花了半个月的一个成果-ATmega16 and DDS-based signal generator code, contains a IAR integrated development environment based on the works, can be directly used IAR open, compile and burn into the single-chip, is I spent a half an outcome
Update : 2025-02-17 Size : 95kb Publisher : 陈晓涛
[VHDL-FPGA-Verilog] dds DL : 0: 使用VHDL硬件描述语言实现了直接频率合成器的制作，并在Altera公司的CycloneII上得到实现，验证了代码的正确性。用户操作可以参照程序中的说明，请使用QuartusII6.0以上版本打开，低版本打开时会有错误提示-Using VHDL hardware description language to achieve a direct frequency synthesizer production, and Altera s CycloneII be realized, to verify the correctness of the code. Users can refer to procedures, please use the above QuartusII6.0 open, low-version will be opened error
Update : 2025-02-17 Size : 103kb Publisher : xx
[OpenGL program] dds DL : 0: 在opengl下加载DDS纹理文件的源程序,支援DXT-1,DXT-3和DXT-5等标准。-Under the load in the opengl texture file DDS source code, support DXT-1, DXT-3 and DXT-5 and other standards.
Update : 2025-02-17 Size : 34kb Publisher : mim
[VHDL-FPGA-Verilog] FPGAdds DL : 0: 用verilog写的DDS程序，请用QuartusII 8.1以上版本打开-DDS program written using verilog, please QuartusII 8.1 or later to open
Update : 2025-02-17 Size : 1.54mb Publisher : 吴恒
[GDI-Bitmap] Test DL : 0: 使用DevIL开源库（原来叫Openil）读取dds（）图像，并转化成jpg格式的图像，是游戏开发、三维纹理处理中非常好的初学例子！-Open source library to use DevIL (originally called Openil) read dds () images, and images into jpg format is game development, three-dimensional texture processing in the example of very good beginner!
Update : 2025-02-17 Size : 2.78mb Publisher : gisupc
[VHDL-FPGA-Verilog] DDS__FPGA DL : 0: 基于FPGA的DDS信号发生器设计，包含Quartus 的工程，打开即可使用，Verilog 语言编写！-The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language! 朗读显示对应的拉丁字符的拼音字典- 查看字典详细内容
Update : 2025-02-17 Size : 90kb Publisher : 小何
[VHDL-FPGA-Verilog] DDS DL : 0: 这是一个dds产生方波、三角波、正弦波的代码。请用Quartus II打开-This is a dds produce square wave, triangle wave, sine wave code. Please open the Quartus II
Update : 2025-02-17 Size : 791kb Publisher : kydchen
[SCM] DDS DL : 0: DDS信号发生器原理图，用protel DXP才能打开。可以做到12M正选信号输出失真很小-DDS signal generator schematic, with protel DXP to open. 12M can do is select a small distortion of the signal output
Update : 2025-02-17 Size : 1.39mb Publisher :
[VC/MFC] About-fpga-use-source-design DL : 0: 关于fpga的使用信号源设计这个包含Quartus 的工程，打开即可使用，Verilog 语言编写！-The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language! -About the use of fpga signal source design contains Quartus project open to use, Verilog language to write!-The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language!
Update : 2025-02-17 Size : 251kb Publisher : 千增源
[MiddleWare] OpenDDS-3.5 DL : 0: openDDS是一个对OMG组织的DDS协议的开源实现，用于分布式的实时发布/订阅系统-openDDS is an open source implementation of the OMG s DDS protocol for distributed real-time publish/subscribe systems
Update : 2025-02-17 Size : 28.26mb Publisher : liuwanjie
[assembly language] vftvdr DL : 0: 基于FPGA的DDS信号发生器设计，包含Quartus 的工程，打开即可使用，Verilog 语言编写！-The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language! 朗读显示对应的拉丁字符的拼音字典- 查看字典详细内容-FPGA design, including the Quartus project, open to use, Verilog language!
Update : 2025-02-17 Size : 276kb Publisher : 熊健友