Search - dds sine cosine

[Communication] DDS_VERILOG

Description: 本例给出了DDS的VERIOG的程序事例,可发生正弦\\余弦等波形,适应与通信方面的硬件实现!-the cases presented DDS VERIOG procedures example, can occur sine \\ cosine wave such as, Adaptation and communications hardware realization!
Platform: | Size: 3309 | Author: 陈榧 | Hits:

[Embeded-SCM Develop] DDSforsinandcos

Description: 用VHDL实现的DDS，可输出正弦、余弦波形。将所有文件放在一个工程文件里，再分别生存模块，按原理图连接及可-using VHDL DDS, output sine, cosine wave. All documents will be placed on a project document, respectively survival module, according to diagram and can link
Platform: | Size: 7432 | Author: 何明均 | Hits:

[Communication] DDS_VERILOG

Description: 本例给出了DDS的VERIOG的程序事例,可发生正弦\余弦等波形,适应与通信方面的硬件实现!-the cases presented DDS VERIOG procedures example, can occur sine \ cosine wave such as, Adaptation and communications hardware realization!
Platform: | Size: 3072 | Author: 陈榧 | Hits:

[Embeded-SCM Develop] DDSforsinandcos

Description: 用VHDL实现的DDS，可输出正弦、余弦波形。将所有文件放在一个工程文件里，再分别生存模块，按原理图连接及可-using VHDL DDS, output sine, cosine wave. All documents will be placed on a project document, respectively survival module, according to diagram and can link
Platform: | Size: 7168 | Author: 何明均 | Hits:

[VHDL-FPGA-Verilog] DDS_all

Description: 这个是相当不错的EDA编程，是电子设计大赛准备期间我引以为自豪的一个，能产生正弦，余弦，方波（可调占空比），三角波，锯齿波以及各种叠加波形，可以自行设置。-The EDA is a very good programming, is the Electronic Design Competition during the preparation I was proud to one capable of producing sine, cosine, square wave (variable duty cycle), triangle wave, sawtooth wave and a variety of superimposed waveforms, can be设置.
Platform: | Size: 2234368 | Author: 谢飞 | Hits:

[VHDL-FPGA-Verilog] dds_bate4[1].1

Description: 在quartus软件下用VHDL语言实现DDS，可产生正弦，余弦，方波，三角波以及锯齿波。-In the Quartus software using VHDL language realize DDS, can generate sine, cosine, square, triangle and sawtooth waves.
Platform: | Size: 3014656 | Author: 崔浩然 | Hits:

[Windows Develop] SINV1.4

Description: 计算正弦余弦表，可用作数字合成时的正弦表（DDS）-Calculate sine cosine table can be used as DDS
Platform: | Size: 8192 | Author: xumin | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 这是一个任意频率的正弦信号发生器，具有可改变输出信号频率，输出信号相位，任意转换输出信号类型（正弦、余弦、锯齿波、方波），屏幕可分别显示用户设定的信号频率与输出信号检测频率。-This is an arbitrary frequency sinusoidal signal generator, with can change the output signal frequency, the output signal phase, arbitrary conversion output signal types (sine, cosine, sawtooth, square wave), the screen showed the user can set the signal frequency and Output signal detection frequency.
Platform: | Size: 1987584 | Author: 紫郢寒光 | Hits:

[VHDL-FPGA-Verilog] cordic

Description: 该程序使用Verilog语言，可以生成dds正余弦信号-The program uses the Verilog language, can generate sine and cosine signals dds
Platform: | Size: 6144 | Author: 王丽 | Hits:

[VHDL-FPGA-Verilog] Wave

Description: 波形发生器可产生正弦波余弦波方波由DDS原理产生-Cosine waveform generator can produce sine wave square wave generated by the DDS principle
Platform: | Size: 3072 | Author: 何恒盛 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 数字频率合成器，生成所需频率的正弦波和余弦波-Digital frequency synthesizer to generate the desired frequency sine wave and cosine wave
Platform: | Size: 1024 | Author: 郑策 | Hits:

[VHDL-FPGA-Verilog] dds

Description: dds数字信号发生器，实现1/4rom存储，正弦，余弦，三角波，锯齿波产生，AM调制-the dds digital signal generator, achieve 1/4rom store, generate sine, cosine, triangle wave, sawtooth, AM modulation
Platform: | Size: 783360 | Author: guizi | Hits:

[matlab] DDS__matlab

Description: matlab的DDS仿真，用寻址法获得相关输出频率的正余弦函数以及任意初相的正弦-Matlab the DDS simulation, addressing law related output frequency of the cosine function and an arbitrary initial phase sine
Platform: | Size: 571392 | Author: 尹子墨 | Hits:

[VHDL-FPGA-Verilog] ca_code

Description: nco的产生原理的相关代码；软件无线电、直接数据频率合成器（DDS，Direct digital synthesizer）、快速傅立叶变换（FFT，Fast Fourier Transform）等的重要组成部分，同时也是决定其性能的主要因素之一，用于产生可控的正弦波或余弦波。随着芯片集成度的提高、在信号处理、数字通信领域、调制解调、变频调速、制导控制、电力电子等方面得到越来越广泛的应用-nco the generation principle of the relevant code software radio, direct data frequency synthesizer (DDS, Direct digital synthesizer), Fast Fourier Transform (FFT, Fast Fourier Transform) and other important component, but also determine the performance of the main factors , controllable for generating a sine wave or cosine wave. With the improvement of chip integration, in signal processing, digital communications, modulation and demodulation, frequency control, guidance and control, power electronics, etc. to be more widely applied
Platform: | Size: 1024 | Author: 李毅 | Hits:

[Other Embeded program] AD9854P430

Description: 使用市场上现在广泛应用的AD9854芯片和MSP430单片机进行DDS模块的制作，整个程序使用并行数据传输，能稳定输出0-60M的正余弦信号，可根据需要改变输出信号的幅值-Now on the market and widely used MSP430 microcontroller chip AD9854 DDS module production, the entire program using parallel data transmission, can stabilize output 0-60M sine and cosine signals, according to the need to change the amplitude of the output signal
Platform: | Size: 28672 | Author: 张灵杰 | Hits:

[VHDL-FPGA-Verilog] mydds2

Description: 利用dds产生产生正弦余弦信号的代码，利用的是rom的方式-Generating code using dds sine cosine signal, using the way of rom
Platform: | Size: 1251328 | Author: shaojian | Hits:

[Embeded-SCM Develop] DDSforsinandcos

Description: 用VHDL实现的DDS，可输出正弦、余弦波形。将所有文件放在一个工程文件里，再分别生存模块，按原理图连接及可-using VHDL DDS, output sine, cosine wave. All documents will be placed on a project document, respectively survival module, according to diagram and can link
Platform: | Size: 7168 | Author: suewit | Hits:

[Embeded-SCM Develop] DDSforsinandcos

Description: 用VHDL实现的DDS，可输出正弦、余弦波形。将所有文件放在一个工程文件里，再分别生存模块，按原理图连接及可-using VHDL DDS, output sine, cosine wave. All documents will be placed on a project document, respectively survival module, according to diagram and can link
Platform: | Size: 7168 | Author: ntexpa | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 利用ISE中的ip核产生正弦和余弦波形，包含有test测试文件-ISE ip core cosine sine testbench
Platform: | Size: 5760000 | Author: dfdqzp | Hits:

[Other] DDS

Description: DDS的字长决定了正弦/余弦基准信号样点的个数和所产生频率信号的量化精度。最小频率间隔决定了DDS所能产生信号的最小频率。DDS所产生信号的频率为最小频率间隔的整数倍。(The word length of the DDS determines the number of sample points of the sine / cosine reference signal and the quantization accuracy of the generated frequency signals. The minimum frequency interval determines the minimum frequency that the DDS can generate. The frequency of the signal generated by the DDS is an integer multiple of the minimum frequency interval.)
Platform: | Size: 2048 | Author: YkY101 | Hits:

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[Communication] DDS_VERILOG

[Embeded-SCM Develop] DDSforsinandcos

[Communication] DDS_VERILOG

[Embeded-SCM Develop] DDSforsinandcos

[VHDL-FPGA-Verilog] DDS_all

[VHDL-FPGA-Verilog] dds_bate4[1].1

[Windows Develop] SINV1.4

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] cordic

[VHDL-FPGA-Verilog] Wave

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] dds

[matlab] DDS__matlab

[VHDL-FPGA-Verilog] ca_code

[Other Embeded program] AD9854P430

[VHDL-FPGA-Verilog] mydds2

[Embeded-SCM Develop] DDSforsinandcos

[Embeded-SCM Develop] DDSforsinandcos

[VHDL-FPGA-Verilog] DDS

[Other] DDS

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