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[
VHDL-FPGA-Verilog
]
ddsfinal1
Description:
verilog语言实现的dds代码，并行通信，生成四种波形，大赛编写的代码，modelsim仿真-verilog language dds code,modelsim debug
Platform:
|
Size:
1137664
|
Author:
杨天
|
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