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[VHDL-FPGA-Verilog] user_logic_VGA_Controller

Description: user_logic_VGA_Controller，适合于DE2开发板，把这个文件夹放在工程目录之中，就可以在SOPC里直接添加VGA_Controller IP核了，很方便使用。-user_logic_VGA_Controller. suitable for Dictyophora development board, this folder on the project directory, it can be added directly SOPC Lane VGA_Controller IP core, very convenient to use.
Platform: | Size: 70656 | Author: 曾 | Hits:

[Other Embeded program] VGA_Controller

Description: 在AlTEA的DE2平台上用VerilogHDL实现的VGA控制模块-AlTEA in the DE2 platform with VerilogHDL achieve VGA Control Module
Platform: | Size: 1024 | Author: luoxi | Hits:

[Other Embeded program] Binary_VGA_Controller

Description: DE2板子附带的VGA IPCORE 有兴趣的朋友可以下载-DE2 board VGA IPCORE accompanying friends who are interested can download
Platform: | Size: 79872 | Author: huang | Hits:

[Embeded-SCM Develop] Binary_VGA_Controller

Description: VGA的IP核，可直接用于nios II的应用里，在DE2板子直接使用-VGA s IP core, can be used directly in nios II applications, the direct use in the DE2 board
Platform: | Size: 79872 | Author: 沈克镇 | Hits:

[Other] de2_vga

Description: altera de2开发板上的vga控制器源码-the development of altera de2 board vga controller source
Platform: | Size: 158720 | Author: 李涛 | Hits:

[Picture Viewer] VGAcontroler_for_Sopc_Builder

Description: altera公司的sopc builder VGA 控制器设计-altera company sopc builder VGA controller design
Platform: | Size: 94208 | Author: Morgan | Hits:

[VHDL-FPGA-Verilog] Binary_VGA_Controller

Description: de2 vga控制器，也可用于其他板子开发-de2 vga controller board can also be used for other development
Platform: | Size: 79872 | Author: 陈斌 | Hits:

[VHDL-FPGA-Verilog] DE2_VGA3

Description: The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until it hits the pixel at the center. It then sticks and a new walker is started randomly at one of the 4 corners of the screen. The random number generators for x and y steps are XOR feedback shift registers (see also Hamblen, Appendix A). The VGA driver, PLL, and reset controller from the DE2 CDROM are necessary to compile this example. Note that you must push KEY0 to start the state machine. -The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until it hits the pixel at the center. It then sticks and a new walker is started randomly at one of the 4 corners of the screen. The random number generators for x and y steps are XOR feedback shift registers (see also Hamblen, Appendix A). The VGA driver, PLL, and reset controller from the DE2 CDROM are necessary to compile this example. Note that you must push KEY0 to start the state machine.
Platform: | Size: 1275904 | Author: Donghua Gu | Hits:

[VHDL-FPGA-Verilog] vga_display

Description: VGA controller源码及显示汉字和ascii字符的c代码实例，已在DE2-70上实现-vga_controller source code and c code which can display chinese charactors and ASCII code on the VGA
Platform: | Size: 304128 | Author: | Hits:

[VHDL-FPGA-Verilog] TrackingPresentation_jon

Description: presentation a low cost video tracking algorithm implemented on an Altera DE2 board with Cyclone II processor. System uses a VGA controller and several SG-DMA s-presentation on a low cost video tracking algorithm implemented on an Altera DE2 board with Cyclone II processor. System uses a VGA controller and several SG-DMA s
Platform: | Size: 1514496 | Author: stjohn | Hits:

[VHDL-FPGA-Verilog] VGA2

Description: VGA controller initialy designed for altera DE2 FPGA with 10 bits DAC. probably works with other systems if you have the correct clock source.
Platform: | Size: 2048 | Author: alzemiro | Hits:

[VHDL-FPGA-Verilog] VGA

Description: VGA图像显示控制器的设计，在DE2板子上成功运行显示-the design of VGA image display controller, it have been run on DE2 successfully
Platform: | Size: 2122752 | Author: fhong | Hits:

[Other] VGA_Controller

Description: 由Verilog HDL编写的VGA控制器模块，可用于DE2板子。-For DE2 board VGA controller module written in Verilog HDL.
Platform: | Size: 81920 | Author: bingyang | Hits:

[VHDL-FPGA-Verilog] DE2_NIOS_HOST_MOUSE_VGA

Description: 本代码为DE2开发板例程源码（EP2C35F672C6），项目基于quartus II 9.0（随板光盘为7.2版本以下，在9.0版以上编译会报错）。本项目实现一个USB画笔功能，通过FPGA控制USB口，USB口接上鼠标，通过XGA口外界显示设备，实现显示设备对鼠标移动轨迹的显示。-In this demonstration, we implement a Paintbrush application by using a USB mouse as the input device.This demonstration uses the device port of the Philips ISP1362 chip and the Nios II processor to implement a USB mouse movement detector. We also implemented a video frame buffer with a VGA controller to perform the real-time image storage and display.
Platform: | Size: 2547712 | Author: chenxin | Hits:

[VHDL-FPGA-Verilog] DE2_TV

Description: 本代码为Altera DE2开发板例程源码，（FPGA：EP2C35F672C6）quartus II 9.0以上可以编译（随板源码为7.2以下版本，在9.0以上版本编译会报错）。本代码实现一个音视频播放器TV_BOX。-This demonstration plays video and audio input a DVD player using the VGA output and audio CODEC on the DE2 board. There are two major blocks in the circuit, called I2C_AV_Config and TV_to_VGA. The TV_to_VGA block consists of the ITU-R 656 Decoder, SDRAM Frame Buffer, YUV422 to YUV444, YCrCb to RGB, and VGA Controller.
Platform: | Size: 215040 | Author: chenxin | Hits:

[VHDL-FPGA-Verilog] VGA

Description: basic controller VGS de2-115
Platform: | Size: 1024 | Author: crisalex | Hits:

[VHDL-FPGA-Verilog] Zet-1.3.1

Description: 在单片FPGA上实现九十年代初期PC，可安装Windows3.1及其他DOS系统。SOC中包含以80286(cpu),中断控制器,显示控制器(VGA),声音控制器,PS2(鼠标，键盘)等。是了解计算机历史变迁及学习SOC设计的重要资料！(ZET aims to implement an early 90`s PC on FPGA.Which include a 80286(cpu),interrupt controller,display card(VGA),sound card,PS2 interface .)
Platform: | Size: 2487296 | Author: VectorIII | Hits:

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