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Description: This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static channel and AWGN noise.
The packet include:
1) Packet Builder (Viterbi Encoding, Interleaver, PN generation)
2) Modulator (RRC filter)
3) Demodulator (Matched Filter, RAKE receiver)
4) Receiver (HD or SD) (Deinterleaver, Viterbi Decoder).
You should run "Simulation.m" function that include all modules.
Platform: |
Size: 10240 |
Author: 李南 |
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Description: 维特比译码的C程序，专门用于卷积码的解码！希望对大家有所帮助！-Viterbi decoding C program devoted to convolutional code decoder! We want to help!
Platform: |
Size: 14336 |
Author: 王建 |
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Description: 维特比解码器低功耗设计verilog编码完整的程序可直接用-Viterbi decoder low power design Verilog coding complete procedures can be used directly
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Size: 386048 |
Author: 杨艺 |
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Description: 通信系统的仿真,Viterbi译码可用于卷积码等的译码解决方案,可以用于通信领域,本例子给出了基于matlab的程序,可用于实际的仿真!-communications system simulation, Viterbi decoder can be used as a convolutional code decoding solution, communications can be used, the example is given of the procedures based on Matlab can be used for actual simulation!
Platform: |
Size: 1024 |
Author: 陈榧 |
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Description: Turbo Decoder Release 0.3
* Double binary, DVB-RCS code
* Soft Output Viterbi Algorithm
* MyHDL cycle/bit accurate model
* Synthesizable VHDL model
-Turbo Decoder Release 0.3* Double binary, DVB-RCS code* Soft Output Viterbi Algorithm* M yHDL cycle/bit accurate model* Synthesizable VHDL model
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Size: 154624 |
Author: |
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Description: viterbi译码器（2.1.7），里面什么都有，测试模块，编码模块和译码模块-Viterbi Decoder (2.1.7), which has everything, testing modules, Encoding and decoding module module
Platform: |
Size: 82944 |
Author: liu |
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Description: viterbi decoder , use verilog HDL language.-Viterbi decoder, use verilog HDL language.
Platform: |
Size: 44032 |
Author: 林四昆 |
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Description: 三篇关于Viterbi FPGA编译码器的优化设计文档：
1、Viterbi译码器的FPGA设计实现与优化.pdf
2、Viterbi译码器的低功耗设计.pdf
3、基于FPGA的高速并行Viterbi译码器的设计与实现.pdf-3 on the Viterbi FPGA optimization codecs design documents: 1, Viterbi decoder FPGA Design Implementation and Optimization. Pdf2, Viterbi decoder, low-power design. Pdf3, high-speed FPGA-based parallel Viterbi decoder Design and Implementation. pdf
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Size: 451584 |
Author: helei_zju |
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Description: 卷积码的维特比译码，约束长度为9，分别采用硬判决和软判决实现-Convolutional code Viterbi decoder, constraint length of 9, respectively, using hard-decision and realize soft-decision
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Size: 11264 |
Author: jishanyi |
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Description: Convolutional(2,1,6) Encoder and soft decision Viterbi Decoder
刚才上载的有错误,已修正-Convolutional (2,1,6) Encoder and soft decision Viterbi Decoder just uploaded a mistake, has been amended
Platform: |
Size: 1024 |
Author: huang |
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Description: 介绍了viterbi译码器的编解码器的设计，包括decoder.v,encoder.v.control.v,ram.v等，压缩 包里面有pdf说明-Introduced a viterbi decoder codec design, including decoder.v, encoder.v.control.v, ram.v and so on, there are pdf compression package description
Platform: |
Size: 62464 |
Author: yaoyongshi |
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Description: 强烈推荐好用的卷积码编码，维特比译码和软判决，本代码简易可行。-Strongly recommend use of the convolutional code encoder, Viterbi decoder and soft decision, the code simple and feasible.
Platform: |
Size: 3072 |
Author: 胡卓 |
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Description: 基于MATLAB的2_1_7_维特比译码器的并行算法实现-MATLAB-based Viterbi decoder 2_1_7_ parallel algorithm
Platform: |
Size: 311296 |
Author: 罗青锋 |
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Description: Viterbi Algorithm & Viterbi Decoder Matlab Code.(Provided both soft & hard decision ability). Note: The main function is viterbi.m
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Size: 3072 |
Author: Nick |
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Description: 基于XilinxFPGA的高速Viterbi回溯译码器-Based on retrospective XilinxFPGA high-speed Viterbi decoder
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Size: 198656 |
Author: mediative |
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Description: 维特比译码器的asic设计的相关论文-Viterbi Decoder asic design related articles
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Size: 277504 |
Author: mediative |
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Description: Viterbi译码器的FPGA实现代码,来在国外大学论坛.-Viterbi decoder implementation of the FPGA code to the Forum at foreign universities.
Platform: |
Size: 8192 |
Author: 蔡敏 |
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Description: verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
Platform: |
Size: 3072 |
Author: xiongherui |
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Description: Viterbi译码器工程,MATLAB环境-Viterbi decoder works, MATLAB environment
Platform: |
Size: 5120 |
Author: ro02150400 |
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Description: 卷积码编码和viterbi译码的matlab 实现(A matlab implementation of a convolutional encoder and a Viterbi decoder)
Platform: |
Size: 4096 |
Author: 三年以后
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