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[Crack Hack] 高级加密算法

Description: AES加密和解密源码！-AES encryption and decryption source!
Platform: | Size: 101376 | Author: 古月 | Hits:

[Other] SC-DSC

Description: 数字通信系统的设计及其性能和所传输的数字信号的统计特性有关。所谓 加扰技术，就是不增加多余度而扰乱信号，改变数字信号的统计特性，使其近 似于白噪声统计特性的一种技术。这种技术的基础是建立在反馈移位寄存器序 列（伪随机序列）理论之上的。解扰是加扰的逆过程，恢复原始的数字信号。 如果数字信号具有周期性，则信号频谱为离散的谱线，由于电路的非线 性，在多路通信系统中，这些谱线对相邻信道的信号造成串扰。而短周期信号 经过扰码器后，周期序列变长，谱线频率变低，产生的非线性分量落入相邻信 道之外，因此干扰减小。 在有些数字通信设备中，从码元“0”和“1”的交变点提取定时信息，若 传输的数字信号中经常出现长的“1”或“0”游程，将影响位同步的建立和保 持。而扰码器输出的周期序列有足够多的“0”、“1”交变点，能够保证同步 定时信号的提取。 -digital communication system design and performance and the transmission of digital signals on the statistical characteristics. The so-called scrambling technology is not to increase the degree to disrupt redundant signal, digital signal change the statistical properties it is similar to white noise statistical characteristics of a technology. This technology is based on feedback shift register sequences (pseudo-random sequence) of the above theory. Decryption is the reverse of the scrambling process, the restoration of the original digital signal. If the digital signal is cyclical, the signal spectrum of discrete lines, as the nonlinear circuit, in multi-channel communication system, these lines of the adjacent channel signal causing crosstalk. And the short-cycle signal after scrambling
Platform: | Size: 113664 | Author: 葛岭泉 | Hits:

[VHDL-FPGA-Verilog] md5

Description: MD5 算法在Xilinx FPGA上的实现，希望对大家有用。-MD5 algorithm in Xilinx FPGA Implementation, in the hope that useful to everyone.
Platform: | Size: 10240 | Author: 张开文 | Hits:

[VHDL-FPGA-Verilog] AES_RTL

Description: 使用Verilog HDL 實現AES硬體加解密-Realize the use of Verilog HDL hardware AES encryption and decryption
Platform: | Size: 15360 | Author: 林夢魔 | Hits:

[Crack Hack] mos_des

Description: 这是一个用VHDL语言实现了DES加密功能的程序，由于DES加密的模式，解密时需把密要倒置-This is a VHDL language with the DES encryption process, as a result of the mode of DES encryption, decryption is required to close to the inverted
Platform: | Size: 27648 | Author: liyajun | Hits:

[VHDL-FPGA-Verilog] inverter

Description: rc5的decryption，同样带state machine，同样有四个状态-RC5 of decryption, with the same state machine, the same four state
Platform: | Size: 2048 | Author: laSiA | Hits:

[VHDL-FPGA-Verilog] RC5_inv

Description: 不带state machine的decryption of rc5-State machine without the decryption of rc5
Platform: | Size: 1024 | Author: laSiA | Hits:

[Crack Hack] DES_Verilog

Description: 这是我用Verilog写的DES加解密程序,准确的说这是一份实验报告,里面不但有程序还有简单的注释[主要是针对仿真的波形的],我主要写的是主控部分,密钥生成部分参考了下版原康宏的程序.该程序即可加密也可解密,选用CycloneII器件即能跑到100Mhz以上.-This is what I used to write Verilog the DES encryption and decryption procedures, accurate to say that this is a test report, which not only have a simple Notes program [is mainly directed against the waveform simulation], I write is the main control part key generation is partly based on the next version of the original Yasuhiro procedures. The program can also be encrypted can be decrypted, CycloneII optional devices which can run more than 100Mhz.
Platform: | Size: 296960 | Author: jesse | Hits:

[Crack Hack] IDEA_DE_TOP

Description: IDEA解密运算模块，运算速率100Mbps，请大家参考-IDEA decryption computing module, computing speed 100Mbps, please refer to
Platform: | Size: 9216 | Author: 刘文庆 | Hits:

[Crack Hack] RIJNDAEL_DE_TOP

Description: AES解密运算模块，运算速率100Mbps，请大家参考-AES decryption computing module, computing speed 100Mbps, please refer to
Platform: | Size: 19456 | Author: 刘文庆 | Hits:

[Crack Hack] rc5decstmac

Description: RC5 decryption algorithm implementation, using vhdl, with state machine implementation, use ieee papers for more detailed description.
Platform: | Size: 2048 | Author: hatela | Hits:

[Crack Hack] t3_enc

Description: triple des encryption decryption
Platform: | Size: 8426496 | Author: mohamed | Hits:

[Speech/Voice recognition/combine] vongrunigen

Description: 语音信号处理，关于语音加密和解密的一个例子-Speech signal processing, voice encryption and decryption on an example of
Platform: | Size: 69632 | Author: 子君 | Hits:

[Crack Hack] AES_verilog

Description: AES 128bit数据,128bit密钥加解密的verilog语言实现-AES 128bit data, 128bit key encryption and decryption of the verilog language implementation
Platform: | Size: 79872 | Author: 刘蕊丽 | Hits:

[Program doc] cunzip

Description: AES CODE FOR DECRYPTION
Platform: | Size: 12288 | Author: sruthi | Hits:

[VHDL-FPGA-Verilog] rsa_IN_vhdl

Description: FULL SIMOLATION IN VHDL FOR RSA DECRYPTION
Platform: | Size: 2019328 | Author: HIMANSHU SINGH | Hits:

[Crack Hack] HMAC-MD5

Description: HMAC — MD 5算法的硬件实现，可以对初学者有一定得帮助。-HMAC- MD 5 algorithm for hardware implementation
Platform: | Size: 179200 | Author: zhangchaoqi | Hits:

[Crack Hack] DESsuanfa

Description: DES的加解密算法的实现，无错，非常适合毕业设计运用-DES encryption and decryption algorithm, error-free
Platform: | Size: 13312 | Author: longli | Hits:

[VHDL-FPGA-Verilog] aes_decrypt

Description: This the Top Module for AES Decryption algorithm-This is the Top Module for AES Decryption algorithm
Platform: | Size: 3072 | Author: Syed Shafi | Hits:

[VHDL-FPGA-Verilog] decryption

Description: AES decryption in VHDL!! Wit LCD controls
Platform: | Size: 12288 | Author: manishrb | Hits:
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